106 patents
Page 2 of 6
Utility
Semiconductor Device Including Superlattice with O18 Enriched Monolayers
1 Dec 22
A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers.
Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
Filed: 26 May 21
Utility
Method for Making Semiconductor Device Including a Superlattice Providing Metal Work Function Tuning
1 Dec 22
A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and forming a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice.
ROBERT J. MEARS, HIDEKI TAKEUCHI
Filed: 18 May 22
Utility
Method for Making Semiconductor Device Including Superlattice with O18 Enriched Monolayers
1 Dec 22
A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers.
MAREK HYTHA, Nyles Wynn Cody, Keith Doran Weeks
Filed: 26 May 21
Utility
Semiconductor Device Including a Superlattice Providing Metal Work Function Tuning
24 Nov 22
A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice.
ROBERT J. MEARS, HIDEKI TAKEUCHI
Filed: 18 May 22
Utility
Methods for Making Bipolar Junction Transistors Including Emitter-base and Base-collector Superlattices
17 Nov 22
A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein.
RICHARD BURTON
Filed: 26 Jul 22
Utility
Bipolar Junction Transistors Including Emitter-base and Base-collector Superlattices
17 Nov 22
A bipolar junction transistor (BJT) may include a substrate defining a collector region therein.
RICHARD BURTON
Filed: 26 Jul 22
Utility
Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
3 Nov 22
A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
Filed: 21 Apr 21
Utility
Method for Making Semiconductor Device Including a Superlattice and Enriched Silicon 28 Epitaxial Layer
27 Oct 22
A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer.
MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
Filed: 21 Apr 21
Utility
Semiconductor device including a superlattice and providing reduced gate leakage
11 Oct 22
A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°.
Hideki Takeuchi, Yung-Hsuan Yang
Filed: 11 Jun 20
Utility
Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
8 Sep 22
A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice.
HIDEKI TAKEUCHI, ROBERT J. MEARS
Filed: 3 Mar 22
Utility
Methods for Making Radio Frequency (RF) Semiconductor Devices Including a Ground Plane Layer Having a Superlattice
8 Sep 22
A method for making a radio frequency (RF) semiconductor device may include forming an RF ground plane layer on a semiconductor-on-insulator substrate and including a conductive superlattice.
Hideki Takeuchi, Robert J. Mears
Filed: 3 Mar 22
Utility
Vertical Semiconductor Device with Enhanced Contact Structure and Associated Methods
8 Sep 22
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench.
ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
Filed: 23 May 22
Utility
Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
6 Sep 22
A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein.
Richard Burton
Filed: 26 Jun 20
Utility
Bipolar junction transistors including emitter-base and base-collector superlattices
6 Sep 22
A bipolar junction transistor (BJT) may include a substrate defining a collector region therein.
Richard Burton
Filed: 26 Jun 20
Utility
Method for making superlattice structures with reduced defect densities
30 Aug 22
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 14 Sep 20
Utility
Semiconductor Device Including a Superlattice and an Asymmetric Channel and Related Methods
28 Jul 22
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
HIDEKI TAKEUCHI, RICHARD BURTON, YUNG-HSUAN YANG
Filed: 12 Apr 22
Utility
Vertical semiconductor device with enhanced contact structure and associated methods
12 Jul 22
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner.
Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
Filed: 23 Nov 20
Utility
Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
7 Jun 22
A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides.
Robert John Stephenson
Filed: 10 Apr 19
Utility
Semiconductor device including a superlattice and an asymmetric channel and related methods
10 May 22
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
Hideki Takeuchi, Richard Burton, Yung-Hsuan Yang
Filed: 21 Apr 20
Utility
Method for Making a Semiconductor Device Using Superlattices with Different Non-semiconductor Thermal Stabilities
6 Jan 22
A method for making a semiconductor device may include forming first and second superlattices adjacent a semiconductor layer.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS
Filed: 1 Jul 21