106 patents
Page 5 of 6
Utility
Method for Making Semiconductor Device Including Body Contact Dopant Diffusion Blocking Superlattice to Reduce Contact Resistance
20 May 20
A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region.
HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Method for Making a Finfet Including Source and Drain Dopant Diffusion Blocking Superlattices to Reduce Contact Resistance
20 May 20
A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween.
HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Semiconductor Device with Metal-semiconductor Contacts Including Oxygen Insertion Layer to Constrain Dopants and Related Methods
20 May 20
A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer.
DANIEL CONNELLY, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Method for Making a Finfet Having Reduced Contact Resistance
20 May 20
A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween.
HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS
Filed: 15 Nov 18
Utility
Method for Making Semiconductor Device Including Source/drain Dopant Diffusion Blocking Superlattices to Reduce Contact Resistance
20 May 20
A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween.
HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS
Filed: 15 Nov 18
Utility
Semiconductor Device Including Body Contact Dopant Diffusion Blocking Superlattice Having Reduced Contact Resistance
20 May 20
A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region.
HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Method for Making a Semiconductor Device Including a Superlattice Having Nitrogen Diffused Therein
29 Apr 20
A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, LOUIS NICHOLAS HUTTER, III
Filed: 30 Oct 18
Utility
Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
27 Apr 20
A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate.
Kalipatnam Vivek Rao
Filed: 12 Jun 18
Utility
CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
6 Apr 20
A CMOS image sensor may include a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first semiconductor chip in a stack and including image processing circuitry electrically connected to the readout circuitry.
Yi-Ann Chen, Abid Husain, Hideki Takeuchi
Filed: 14 Dec 17
Utility
Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
30 Mar 20
A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip including image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip in a stack.
Yi-Ann Chen, Abid Husain, Hideki Takeuchi
Filed: 14 Dec 17
Utility
Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
30 Mar 20
A method for making a CMOS image sensor may include forming a first semiconductor chip including an array of image sensor pixels and readout circuitry electrically connected thereto, forming a second semiconductor chip comprising image processing circuitry electrically connected to the readout circuitry, and coupling the first semiconductor chip and the second semiconductor chip together in a stack.
Yi-Ann Chen, Abid Husain, Hideki Takeuchi
Filed: 14 Dec 17
Utility
Method for making a semiconductor device having reduced contact resistance
16 Mar 20
A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Semiconductor Device Including Superlattice Structures with Reduced Defect Densities
4 Mar 20
A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers.
Keith Doran WEEKS, Nyles Wynn CODY, Marek HYTHA, Robert J. MEARS, Robert John STEPHENSON
Filed: 29 Aug 18
Utility
Method for Making Superlattice Structures with Reduced Defect Densities
4 Mar 20
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 29 Aug 18
Utility
Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
2 Mar 20
A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
2 Mar 20
A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Semiconductor device including superlattice structures with reduced defect densities
17 Feb 20
A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 29 Aug 18
Utility
CMOS image sensor including pixels with read circuitry having a superlattice
6 Jan 20
A CMOS image sensor may include an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement.
Yi-Ann Chen, Abid Husain, Hideki Takeuchi
Filed: 14 Dec 17
Utility
Method for making CMOS image sensor including pixels with read circuitry having a superlattice
6 Jan 20
A method for making a CMOS image sensor may include forming an active pixel sensor array including pixels, each including a photodiode and read circuitry coupled to the photodiode and including transistors defining a 4T cell arrangement.
Yi-Ann Chen, Abid Husain, Hideki Takeuchi
Filed: 14 Dec 17
Utility
Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
4 Nov 19
A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 8 Mar 18