106 patents
Page 4 of 6
Utility
Method for Making Superlattice Structures with Reduced Defect Densities
30 Dec 20
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON
Filed: 13 Sep 20
Utility
Method for making a semiconductor device including enhanced contact structures having a superlattice
28 Dec 20
A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench.
Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
Filed: 7 Mar 19
Utility
Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
28 Dec 20
A method for making semiconductor device may include forming a hyper-abrupt junction region on a substrate and including a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 16 Jul 19
Utility
Method for making a varactor with hyper-abrupt junction region including a superlattice
14 Dec 20
A method for making a semiconductor device may include forming a hyper-abrupt junction region on a substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 16 Jul 19
Utility
Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
30 Nov 20
A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
23 Nov 20
A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
16 Nov 20
A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
16 Nov 20
A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer.
Daniel Connelly, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Method for making a FINFET having reduced contact resistance
16 Nov 20
A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Varactor with hyper-abrupt junction region including a superlattice
16 Nov 20
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 16 Jul 19
Utility
Semiconductor devices including hyper-abrupt junction region including a superlattice
2 Nov 20
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 16 Jul 19
Utility
Varactor with hyper-abrupt junction region including spaced-apart superlattices
2 Nov 20
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate.
Richard Burton, Marek Hytha, Robert J. Mears
Filed: 16 Jul 19
Utility
Method for Making a Semiconductor Device Including a Superlattice and an Asymmetric Channel and Related Methods
28 Oct 20
A method for making a semiconductor device may include forming spaced apart first and second doped regions in a substrate.
HIDEKI TAKEUCHI, Richard Burton, Yung-Hsuan Yang
Filed: 20 Apr 20
Utility
Semiconductor Device Including a Superlattice and an Asymmetric Channel and Related Methods
28 Oct 20
A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate.
HIDEKI TAKEUCHI, Richard Burton, Yung-Hsuan Yang
Filed: 20 Apr 20
Utility
Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
26 Oct 20
A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween.
Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
Filed: 15 Nov 18
Utility
Method for making superlattice structures with reduced defect densities
19 Oct 20
A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 29 Aug 18
Utility
Semiconductor device including enhanced contact structures having a superlattice
14 Sep 20
A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench.
Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J Mears, Erwin Trautmann
Filed: 7 Mar 19
Utility
Inverted T channel field effect transistor (ITFET) including a superlattice
31 Aug 20
A semiconductor device may include a substrate and an inverted T channel on the substrate and including a superlattice.
Robert John Stephenson
Filed: 9 Apr 19
Utility
Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface
10 Aug 20
A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions.
Robert John Stephenson, Scott A. Kreps, Robert J. Mears, Kalipatnam Vivek Rao
Filed: 16 Aug 18
Utility
Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice
27 Jul 20
A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor.
Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
Filed: 8 Mar 18