11728 patents
Page 19 of 587
Utility
Optimization Technique for Modular Multiplication Algorithms
14 Dec 23
Methods and apparatus for optimization techniques for modular multiplication algorithms.
Erdinc OZTURK, Kirk S. YAP, Tomasz KANTECKI
Filed: 24 Aug 23
Utility
Hardware Software Communication Channel to Support Direct Programming Interface Methods on Fpga-based Prototype Platforms
14 Dec 23
Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation.
Renu Patle, Hanmanthrao Patli, Rakesh Mehta, Hagay Spector, Ivan Herrera Mejia, Fylur Rahman Sathakathulla, Gowtham Raj Karnam, Mohsin Ali, Sahar Sharabi, Abraham Halevi Fraenkel, Eyal Pniel, Ehud Cohn, Raghav Ramesh Lakshmi, Altug Koker
Filed: 14 Jun 22
Utility
2qa1ns1vr5uyysaw8qezagf200e3hurwc9z6tt4lvichxvkuwoqgb
14 Dec 23
In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region.
Mathew Lowes, Martin Licht, Jonathan Combs
Filed: 14 Jun 22
Utility
9hd78vwjwhdhqmu p8gk055w22ao
14 Dec 23
Deep neural networks (DNNs) with budding ensemble architectures may be trained using diversity loss.
Qutub Syed Sha, Neslihan Kose Cihangir, Rafael Rosales
Filed: 28 Aug 23
Utility
9kwnn9amq5pn0hrpv26gabk91g0v9o0dxxdyfp3s
14 Dec 23
Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).
Niall D. MCDONNELL, Ambalavanar ARULAMBALAM, Te Khac MA, Surekha PERI, Pravin PATHAK, James CLEE, An YAN, Steven POLLOCK, Bruce RICHARDSON, Vijaya Bhaskar KOMMINENI, Abhinandan GUJJAR
Filed: 24 Aug 23
Utility
fj0jghr3tzlurzd9759n16 tpd5l3u2t330qmak
14 Dec 23
An apparatus is described.
Ram KRISHNAMURTHY, Gregory K. CHEN, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL
Filed: 24 Aug 23
Utility
3h6urku51eltj2306068j3kt262cs2lpnceg1pwq2abvbandp8
14 Dec 23
Technologies for managing accelerator resources include a cloud resource manager to receive accelerator usage information from each of a plurality of node compute devices and task parameters of a task to be performed.
Malini K. BHANDARU, Sundar Nadathur, Joseph Greeco, Roman DOBOSZ, Yongfeng DU
Filed: 25 Aug 23
Utility
w12cqfbnco0oxhusf6y519r27y y363y5rekuumcpsz0sbmxhy66ex135
14 Dec 23
One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.
Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
Filed: 25 Aug 23
Utility
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14 Dec 23
A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided.
Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak K. Gupta
Filed: 10 Aug 23
Utility
ekhu4fd7d9i9ozv2nxsfbklfv1g
14 Dec 23
The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.
Sergej Deutsch, Christoph Dobraunig, Rajat Agarwal, David M. Durham, Santosh Ghosh, Karanvir Grewal, Krystian Matusiewicz
Filed: 22 Dec 22
Utility
1ii92jd 5zgyhct9w7a9f9vrop2mwq3x5qzd8910rng8ux39
14 Dec 23
Techniques for thin-film resistors in vias are disclosed.
Benjamin T. Duong, Brian P. Balch, Kristof Darmawikarta, Darko Grujicic, Suddhasattwa Nad, Xing Sun, Marcel A. Wall, Yi Yang
Filed: 10 Jun 22
Utility
nnu7nj1gfvcprt3zt3z6hnqpobyc4cgoqp6byrw84946zs7
14 Dec 23
Interconnect via metal-insulator-metal (MIM) fuse for integrated circuitry.
Yao-Feng Chang
Filed: 8 Jun 22
Utility
77rst a42ep6xy37p9zpc4l2bq
14 Dec 23
A memory array including integrated word line (WL) contact structures are disclosed.
Nanda Kumar Chakravarthi, Kwame Nkrumah Eason, Abhinav Tripathi, Ebony Lynn MAYS, Jessica Sevanne Kachian, Ralf Buengener
Filed: 18 Aug 23
Utility
1e4zsaci fh6os61licy9cdep7acjf48y6av9rbmmfwemfs
14 Dec 23
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices.
Nicholas A. Thomson, Kalyan C. Kolluru, Adam Clay Faust, Frank Patrick O'Mahony, Ayan Kar, Rui Ma
Filed: 29 Aug 23
Utility
l88jh59wfdyi9mx7xk40z7ofts4zjwjtrf0lfdahfqaed8derrn9j
14 Dec 23
Capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed.
Thomas Sounart, Kaan Oguz, Neelam Prabhu Gaunkar, Tristan Tronic
Filed: 8 Jun 22
Utility
idy3x 663gldxb8whpz2swtxoa8a504v81ranzcvo
14 Dec 23
An integrated circuit structure includes a second device stacked vertically above a first device.
Rohit Galatage, Willy Rachmady, Cheng-Ying Huang, Jami A. Wiedemer, Munzarin F. Qayyum, Nicole K. Thomas, Patrick Morrow, Marko Radosavljevic, Mauro J. Kobrinsky
Filed: 13 Jun 22
Utility
i3gxag1blo28vhk1yamj4l0lqy5xgsvnlixkgpdsjdy65j
14 Dec 23
An integrated circuit structure includes a device including a source region, a drain region, a body laterally between the source and drain regions, and a source contact coupled to the source region.
Rohit Galatage, Willy Rachmady, Subrina Rafique, Nitesh Kumar, Cheng-Ying Huang, Jami A. Wiedemer, Nicloe K. Thomas, Munzarin F. Qayyum, Patrick Morrow, Marko Radosavljevic, Mauro J. Kobrinsky
Filed: 13 Jun 22
Utility
6avfjbqtturgxylg ezsx6uz22rv1idcswahl7e9cmmn24x7
14 Dec 23
Jason A. Mix, Liwei Zhao, Alexander T. Hoang, Sarah Shahraini, Ruth Y. Vidana Morales, Andrew Martwick, Andrea S. Muljono
Filed: 14 Apr 23
Utility
i2fcchtkjuxg3 0vjsu6qfgur6uf88j0u
14 Dec 23
Examples described herein relate to a network interface device.
Md Ashiqur RAHMAN, Rong PAN, Roberto PENARANDA CEBRIAN, Allister ALEMANIA, Pedro YEBENES SEGURA
Filed: 29 Aug 23
Utility
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14 Dec 23
An apparatus to facilitate encoding video data is disclosed.
Junhua Hou, Zhihong Yu, Yesheng Xu, Hongbo Lv, Jiangming Wu
Filed: 24 May 23