20858 patents
Page 3 of 1043
Utility
Packing Machine Learning Models Using Pruning and Permutation
11 Jan 24
An example system includes a processor to prune a machine learning model based on an importance of neurons or weights.
Subhankar PAL, Alper BUYUKTOSUNOGLU, Ehud AHARONI, Nir DRUCKER, Omri SOCEANU, Hayim SHAUL, Kanthi SARPATWAR, Roman VACULIN, Moran BARUCH, Pradip BOSE
Filed: 5 Jul 22
Utility
Multi-stage Knowledge Graph Construction Using Models
11 Jan 24
A knowledge graph is constructed as part of a multi-stage process using pretrained language models.
Igor Melnyk, Pierre L. Dognin, Payel Das
Filed: 8 Jul 22
Utility
Location Recommendation for Micro-climate Management
11 Jan 24
According to one embodiment, a method, computer system, and computer program product for micro-environment management is provided.
Shailendra Moyal, Sarbajit K. Rakshit, Partho Ghosh
Filed: 7 Jul 22
Utility
Self-aligned Bottom Spacer
11 Jan 24
Embodiments of present invention provide a method of forming a transistor structure.
Ruilong Xie, Hemanth Jagannathan, Jay William Strane, Kangguo Cheng
Filed: 5 Jul 22
Utility
Stacked Fet Architecture with Separate Gate Regions
11 Jan 24
A stacked FET architecture includes isolated pockets for replacement metal gates for top and bottom nanosheet field-effect transistors.
Chen Zhang, Tenko Yamashita
Filed: 5 Jul 22
Utility
Structure and Method for Maximizing Air Gap In Back End of the Line Interconnect Through Via Landing Modification
11 Jan 24
An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines.
Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
Filed: 28 Jun 23
Utility
Stacked Vertical Transport Field-effect Transistor Logic Gate Structures with Shared Epitaxial Layers
11 Jan 24
A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.
Tsung-Sheng Kang, Ardasheir Rahman, Tao Li, Su Chen Fan
Filed: 21 Sep 23
Utility
Stacked Field Effect Transistor Contacts
11 Jan 24
A semiconductor device including a first source/drain region (S/D) located on a frontside of a substrate, wherein the first source/drain region has a first width, a second S/D region located on the frontside of the substrate, wherein the second source/drain region is located above the first source drain region, wherein the second source/drain region has second width, wherein the first width is larger than the second width, a first power rail located on a backside of the substrate, a second power rail located on the backside of the substrate, a first connector in contact with the first source/drain region, wherein the first connector is only in contact with a sidewall of the first source/drain region, and a second connector in contact with the second source/drain region, wherein the second connector is in contact with a top surface and a side surface of the second source/drain region.
Junli Wang, Albert M. Chu, Albert M. Young, Chen Zhang, Su Chen Fan, Ruilong Xie
Filed: 7 Jul 22
Utility
Sidewall Epitaxy Encapsulation for Nanosheet I/o Device
11 Jan 24
A method includes forming a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and forming a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device.
Ruqiang Bao, Shogo Mochizuki
Filed: 25 Sep 23
Utility
Hardware-based Key Generation and Storage for Cryptographic Function
11 Jan 24
A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a key-generating instruction.
DEBAPRIYA CHATTERJEE, Silvia Melitta Mueller, Maarten J. Boersma, Martijn Diede Berkers
Filed: 5 Jul 22
Utility
Extend Controller for Multi-tenancy
11 Jan 24
A system may include a memory and a processor in communication with the memory.
Peng Li, Guangya Liu, Xun Pan, Hai Hui Wang, Xiang Zhen Gan, Xin Peng Liu
Filed: 6 Jul 22
Utility
Three-dimensional, Monolithically Stacked Field Effect Transistors Formed on the Front and Backside of a Wafer
11 Jan 24
A semiconductor device fabrication method is provided.
Sung Dae Suk, Somnath Ghosh, Chen Zhang, Junli Wang, Devendra K. Sadana, Dechao Guo
Filed: 25 Sep 23
Utility
Single Diffusion Break
11 Jan 24
Embodiments of present invention provide a semiconductor structure.
Ruilong Xie, CHANRO PARK, Kangguo Cheng, Julien Frougier, Min Gyu Sung
Filed: 8 Jul 22
Utility
Predicting Security Response Impact
11 Jan 24
An approach to predicting the outcome of a computer security response.
Fady Copty
Filed: 25 Sep 23
Utility
Media Recycling and Sanitization
4 Jan 24
Polyester-free magnetic and/or metallic components are obtained from a multicomponent polyester device by reacting the multicomponent polyester device with an amine organocatalyst and/or carboxylic acid salt of same and an alcohol solvent.
Gregory Breyta, Robert David Allen
Filed: 18 Sep 23
Utility
Ring-opening Polymerizations Using a Flow Reactor
4 Jan 24
Techniques regarding the synthesis of one or more polymers through one or more ring-opening polymerizations conducted within a flow reactor and facilitated by one or more anionic catalysts are provided.
Nathaniel H. Park, James L. Hedrick, Victoria A. Piunova, Dmitry Zubarev, Gavin O. Jones, Robert M. Waymouth, Binhong Lin
Filed: 12 Sep 23
Utility
Secure Access Management for Tools Within a Secure Environment
4 Jan 24
A method, system and computer program product for secure access management for tools within a secure environment.
Olgierd Pieczul, Jinhui Wang
Filed: 15 Sep 23
Utility
Stacked Fet Sram
4 Jan 24
A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor.
Ruilong Xie, Carl Radens, Albert M. Chu, Brent A. Anderson, Junli Wang, Julien Frougier, Ravikumar Ramachandran
Filed: 30 Jun 22
Utility
Vertical Ultra-thin PCM Cell
4 Jan 24
Memory cells and methods of forming the same include forming a hole in an interlayer dielectric to expose an end of a conductive top electrode.
Kevin W. Brew, Timothy Mathew Philip, JIN PING HAN, Ching-Tzu Chen, Injo Ok
Filed: 30 Jun 22
Utility
Thermal and Performance Management
4 Jan 24
Described aspects include a system for optimizing performance of a functional circuit unit, a method of optimizing performance of a functional circuit unit, and a computer program product.
Xin Zhang, Shun Zhang, Shaoze Fan, Xiaoxiao Guo, Chuang Gan
Filed: 29 Jun 22