20858 patents
Page 6 of 1043
Utility
Beveled Magneto-resistive Random Access Memory Pillar Structure
28 Dec 23
A memory device includes a magnetic tunnel junction pillar located between, and electrically connected to, a bottom electrode and a top electrode.
Oscar van der Straten, Chih-Chao Yang, Praneet Adusumilli
Filed: 24 Jun 22
Utility
Voltage-swing Method for Carbon Capture Using Porous Carbons
28 Dec 23
A method and system for carbon capture through a voltage-swing is provided.
Binquan Luan, Bruce Gordon ELMEGREEN
Filed: 24 Jun 22
Utility
4uhj5rqc9xo6xk1dkbefizplb450awr53qw0ubah68pqez7xmd
28 Dec 23
Polyester-free cotton is obtained from a fabric and/or fibers containing polyester and cotton by reacting the fabric and/or fibers with an amine organocatalyst and/or carboxylic acid salt of same and an alcohol solvent.
Gregory Breyta, Robert David Allen
Filed: 11 Sep 23
Utility
juz1p1a330edynhx7ub4bhxov54q10nhr3uq xqb
28 Dec 23
A semiconductor device structure and methodology for determining a power consumption of the device structure and to extract accurate real temperatures due to self-heating effects.
HUIMEI ZHOU, MIAOMIAO WANG, Effendi Leobandung
Filed: 24 Jun 22
Utility
mms1vvrqovon3uf6mqcs9p21aqbl7zytalfo3zcb2 ko6pfo9juh4lwmth
28 Dec 23
According to one embodiment, a method, computer system, and computer program product for aiding a user in the preparation and completion of a dish within a social sensory recipe program are provided.
Juel Daniel Raju, Christopher Bryan Barnwell, Romelia H. Flores, Susan Jachin Christian
Filed: 22 Jun 22
Utility
723i3qdn9ux6x8lmxukj4n0wyjkg4b98vg194wtlpq7nq4gz8i 51
28 Dec 23
Aspects of the disclosure include a structure for thermal management of pluggable hardware modules, an optical transceiver, and a method of cooling a pluggable hardware module.
Yuanchen Hu, Sushumna Iruvanti, Philipp K Buchling Rego
Filed: 26 Jun 22
Utility
uptd2n6h7s824ip1997 4h4m0fogr3gg
28 Dec 23
Embodiments of the invention include providing interconnects with two-dimensional free zero line end enclosure.
Ruilong Xie, Albert M. Chu, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Huai Huang
Filed: 23 Jun 22
Utility
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28 Dec 23
A semiconductor structure including a reliable power rail in stacked field effect transistor technology with unequal device footprints is provided that mitigates, and in some cases even eliminates, shorting risks that are typically associated using long bars in advanced logic applications.
Albert M. Young, Albert M. Chu, Junli Wang
Filed: 22 Jun 22
Utility
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28 Dec 23
A semiconductor device is provided.
Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega, Lawrence A. Clevenger, Albert M. Chu, Brent A. Anderson
Filed: 22 Jun 22
Utility
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28 Dec 23
The semiconductor device includes a first metal layer, a second metal layer, a metal plane, a third dielectric layer and a fourth dielectric layer.
Nicholas Anthony Lanzillo, Ruilong Xie, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger
Filed: 22 Jun 22
Utility
mon6otgfd1wljkrg9zfb2p86i2iw5tlqqqqgxo gxpqm9417w5ugl7l12
28 Dec 23
A semiconductor device is provided.
Ruilong Xie, Kisik Choi, Su Chen Fan, Albert M. Young
Filed: 24 Jun 22
Utility
174jty71nrccc8cowsxh61
28 Dec 23
Embodiments are disclosed for a complementary metal oxide semiconductor (CMOS) device.
Carl Radens, Ruilong Xie, Albert M. Chu, Brent A. Anderson
Filed: 27 Jun 22
Utility
tqo4kkm1g67m23fdio5os4yfw0
28 Dec 23
A multi-chip package structure is provided.
Anil Yuksel, Jose A. Hejase, Junyan Tang, Pavel Roy Paladhi, Joshua Myers
Filed: 22 Jun 22
Utility
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28 Dec 23
Embodiments of the invention include a single stack dual channel gate-all-around nanosheet with strained PFET and bottom dielectric isolation NFET.
Julien Frougier, Andrew M. Greene, Shogo Mochizuki, Kangguo Cheng, Ruilong Xie, Heng Wu, Min Gyu Sung, Liqiao Qin, Gen Tsutsui
Filed: 23 Jun 22
Utility
pfj4qey4ykiu98sf8de056yt3 h89utw
28 Dec 23
A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer.
Joshua M. Rubin, Chen Zhang, Tenko Yamashita, Brent A. Anderson
Filed: 23 Jun 22
Utility
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28 Dec 23
Metal-insulator-metal capacitor designs with increased reliability are provided.
Kisik Choi, Paul Charles Jamison, Takashi Ando, Lawrence A. Clevenger, Huimei Zhou, Miaomiao Wang, Ernest Y. Wu
Filed: 28 Jun 22
Utility
3eqscn00evl5emmrkm5xxqj0edk1ez5rb 4be9gelz7t5ibidq556x6gft
28 Dec 23
A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region.
Julien Frougier, Ruilong Xie, Kangguo Cheng, CHANRO PARK, Oleg Gluschenkov
Filed: 27 Jun 22
Utility
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28 Dec 23
A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain.
Heng Wu, Junli Wang, Ruilong Xie, Albert M. Young, Albert M. Chu, Brent A. Anderson, Ravikumar Ramachandran
Filed: 22 Jun 22
Utility
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28 Dec 23
A stacked semiconductor structure including a top transistor stacked above a bottom transistor, and a single gate contact in electrical contact with a top gate conductor of the top transistor and a bottom gate conductor of the bottom transistor.
Su Chen Fan, Stuart Sieg, Xuan Liu, Junli Wang
Filed: 24 Jun 22
Utility
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28 Dec 23
A semiconductor structure includes a common substrate; a first forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate and that has an nFET (n-doped Field Effect Transistor) and a pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the nFET and the pFET; and a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET.
Ruilong Xie, REINALDO VEGA, Julien Frougier, Kangguo Cheng
Filed: 25 Jun 22