20858 patents
Page 5 of 1043
Utility
Work Function Metal Patterning for Nanosheet Cfets
4 Jan 24
Semiconductor devices, and methods of forming the same, include forming a stack of channel layers, including an upper device region and a lower device region.
Ruilong Xie, Chen Zhang, Kangguo Cheng, Juntao Li
Filed: 13 Sep 23
Utility
Self-aligned Backside Connections for Transistors
4 Jan 24
Provided is a semiconductor device.
Brent A. Anderson, Ruilong Xie, Junli Wang, Albert M. Chu
Filed: 29 Jun 22
Utility
Hybrid Buried Power Rail Structure with Dual Front Side and Backside Processing
4 Jan 24
A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface.
Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Ruilong Xie, Lawrence A. Clevenger
Filed: 30 Jun 22
Utility
Self-aligned Backside Gate Contact for Backside Signal Line Integration
4 Jan 24
A semiconductor array structure includes a substrate; a plurality of field effect transistors (FETs) arranged in rows and located on the substrate, each comprising a first source-drain region, a second source-drain region, at least one channel coupling the source-drain regions, and a gate adjacent the at least one channel.
Ruilong Xie, REINALDO VEGA, David Wolpert, Kisik Choi
Filed: 30 Jun 22
Utility
Front End of Line Processing Compatible Thermally Stable Buried Power Rails
4 Jan 24
Semiconductor devices, and methods of their formation, are provided.
Sagarika Mukesh, Christian Lavoie, Daniel Charles Edelstein, Ruilong Xie
Filed: 30 Jun 22
Utility
Metal-insulator-metal Capacitor (Mimcap)-based Physically Unclonable Function
4 Jan 24
An integrated circuit includes a semiconductor substrate; a logic area, located outward of the semiconductor substrate; and a physically unclonable function (PUF) area, located outward of the semiconductor substrate.
Cheng Chi, Takashi Ando, REINALDO VEGA, Praneet Adusumilli
Filed: 30 Jun 22
Utility
Semiconductor Device Interconnect Structure
4 Jan 24
An interconnect system may connect a first semiconductor device with second semiconductor device.
Keiji Matsumoto, Toyohiro Aoki, Takahito Watanabe, RISA MIYAZAWA, Takashi Hisada
Filed: 29 Jun 22
Utility
Co-integration of Gate-all-around Nanosheet Logic Device and Precision Mol Resistor
4 Jan 24
A semiconductor structure that includes a nanosheet logic device (i.e., nFET and/or pFET) co-integrated with a precision middle-of-the-line (MOL) resistor is provided.
Julien Frougier, Sagarika Mukesh, Anthony I. Chou, Andrew M. Greene, Ruilong Xie, Nicolas Jean Loubet, Veeraraghavan S. Basker, Junli Wang, Effendi Leobandung, Jingyun Zhang
Filed: 29 Jun 22
Utility
MULTI-Vt REPLACEMENT METAL GATE BONDED STACKED FETs
4 Jan 24
A semiconductor structure is presented including a first field effect transistor (FET), the first FET including at least a first set of fins and a second set of fins, the first set of fins surrounded by a first work function metal (WFM) and the second set of fins surrounded by a second WFM and a second FET formed directly over the first FET, the second FET including at least a first nanosheet stack and a second nanosheet stack, the first nanosheet stack surrounded by a third WFM and the second nanosheet stack surrounded by a third WFM with dipoles.
Ruqiang Bao, Junli Wang, Dechao Guo, Heng Wu
Filed: 29 Jun 22
Utility
Semiconductor Device with Robust Inner Spacer
4 Jan 24
A semiconductor structure includes a plurality of semiconductor layers vertically stacked over a semiconductor substrate.
Shogo Mochizuki, Juntao Li, Kangguo Cheng
Filed: 30 Jun 22
Utility
Stacked Combsheet Field Effect Transistor
4 Jan 24
An integrated circuit structure includes a first combsheet field effect transistor (FET), which includes: a semiconductor substrate; a first plurality of semiconductor nanosheets that extend along a <101> crystallographic direction and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes; and a semiconductor fin that is integrally attached to the nanosheets, extends along the nanosheets, and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.
Tsung-Sheng Kang, Ruqiang Bao, Curtis S. Durfee, Tao Li
Filed: 30 Jun 22
Utility
Field Effect Transistors with 2-DIMENSIONAL Electron Gas Channels
4 Jan 24
A semiconductor structure that includes a channel region comprising vertically stacked channels of at least two III-V semiconductor material layers having a two dimensional electron gas regions at an interface of the at least two III-V semiconductor material layers; a gate all around (GAA) geometry gate structure present on the channel region; and source and drain regions on opposing sides of the channel region.
Julien Frougier, Kangguo Cheng, Ruilong Xie, Juntao Li, Chanro Park, Oleg Gluschenkov
Filed: 1 Jul 22
Utility
Rechargeable Battery with Hybrid Cathode Comprising Conversion and Intercalation Active Materials
4 Jan 24
A rechargeable battery is disclosed.
Young-Hye Na, Maxwell Giammona, Tsubasa Itakura, Saori Itabashi, Rei Tsukazaki, Katsutoshi Suzuki, Kazunari Takeda
Filed: 30 Jun 22
Utility
Data Protection In Network Environments
4 Jan 24
Computer technology for protecting data security in a computerized system for recommending content to users where, a processing unit generates an identifier for a first data record relating to a user device based on a first machine learning model.
Jin Wang, Lei Gao, A PENG ZHANG, DAN SUN, Jing Zhang, Na Liu, Xun Pan, ZI YUN KANG
Filed: 29 Jun 22
Utility
Edge Node Autonomy
4 Jan 24
A computer-implemented method, an apparatus, and a computer program product for edge node autonomy.
Peng Li, Guang Ya Liu, Xun Pan, Hai Hui Wang, Xiang Zhen Gan
Filed: 29 Jun 22
Utility
Real-time Control of Via Stub Drilling Depth Asymmetry
4 Jan 24
A gang drilling machine for drilling a circuit card includes a pair of n and p master drills that are configured to be aligned in registry with respective n and p test vias of the card; pluralities of n and p minion drills that are configured to be aligned in registry with pluralities of n and p live vias of the card; and a controller that is electrically connected to control the n and p master drills and minion drills, and to send and receive electrical signals to and from the card.
Yanyan Zhang, Mahesh Bohra, Wiren Dale Becker, Nam Huu Pham, Pavel Roy Paladhi, Daniel Mark Dreps, Lloyd Andre Walls
Filed: 30 Jun 22
Utility
Standoff And Support Structures for Reliable Land Grid Array and Hybrid Land Grid Array Interconnects
4 Jan 24
Disclosed herein is a method for producing a land grid array (LGA) socket connector assembly and the resultant assembly.
Mark K. Hoffmeyer, Sarah K. Czaplewski-Campbell, Brian Beaman, Yuet-Ying Yu
Filed: 29 Jun 22
Utility
Quantum Advantage Using Quantum Circuit for Gradient Estimation
28 Dec 23
Described herein are quantum gradient algorithms that result in a quantum advantage over conventional methods.
Nikitas Stamatopoulos, Guglielmo Mazzola, Stefan Woerner, William J. Zeng
Filed: 18 Nov 22
Utility
Decoupling Capacitor Inside Gate Cut Trench
28 Dec 23
An approach to forming a semiconductor device where the semiconductor device includes a first power rail that is connected to a decoupling capacitor by way of a first gate.
REINALDO VEGA, Takashi Ando, Praneet Adusumilli, David Wolpert, Cheng Chi
Filed: 22 Jun 22
Utility
Mram Device with Self-aligned Bottom Electrodes
28 Dec 23
A magnetic tunnel junction (MTJ) stack, where a vertical side surface of a bottom electrode of the MTJ stack is surrounded by an oxide, where the bottom electrode and the oxide are horizontally aligned.
Oscar van der Straten, Lisamarie White, Willie Lester Muchrison, JR., Chih-Chao Yang
Filed: 24 Jun 22