51 patents
Utility
Library Cell Modeling for Transistor-level Test Pattern Generation
3 Mar 22
This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns.
Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
Filed: 27 Aug 20
Utility
Suspect Resolution for Scan Chain Defect Diagnosis
3 Mar 22
This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting.
Grzegorz Mrugalski, Szczepan Urban, Jakub Janicki
Filed: 31 Aug 20
Utility
Deterministic Stellar Built-in Self Test
2 Dec 21
A system for testing a circuit comprises scan chains, a controller configured to generate a bit- inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation.
Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Filed: 21 Mar 19
Utility
Machine Learning-based Classification In Parasitic Extraction Automation for Circuit Design and Verification
12 Aug 21
This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit.
Vasileios Kourkoulos, Lin Du, Renbo Chen
Filed: 12 Feb 20
Utility
Multi-objective Calibrations of Lithography Models
15 Jul 21
A system may include a model calibration engine configured to determine a candidate lithography model set from which to calibrate a lithography model according to multiple objectives, including by initializing a population of parent candidate models, generating child candidate models, merging the parent and child candidate models into a merged population, classifying the candidate models of the merged population into tiers of non-dominated fronts according to respective objective functions for the multiple objectives, determining a subset of the merged population based on the classified tiers, and identifying, as the candidate lithography model set, a Pareto-optimal front of the subset of the merged population determined based on the classified tiers.
Huikan Liu
Filed: 9 Jan 20
Utility
Error-Correcting Code-Assisted Memory Repair
10 Jun 21
A memory-testing circuit configured to perform a test of a memory comprising error-correcting code circuitry comprises repair circuitry configured to allocate a spare row or row block in the memory for a defective row or row block in the memory, a defective row or row block being a row or row block in which a memory word has a number of error bits greater than a preset number, wherein the test of the memory comprises: disabling the error-correcting code circuitry, performing a pre-repair operation, the pre-repair operation comprising: determining whether the memory has one or more defective rows or row blocks, and allocating one or more spare rows or row blocks for the one or more defective rows or row blocks if the one or more spare rows or row blocks are available, and performing a post-repair operation on the repaired memory.
Benoit Nadeau-Dostie
Filed: 9 Dec 20
Utility
Trajectory-Optimized Test Pattern Generation for Built-In Self-Test
27 May 21
A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
Filed: 17 Nov 20
Utility
Adaptive Penalty Term Determinations In Applications of Quantum Computing to Electronic Design Automation Processes
20 May 21
A system may include a quantum model engine configured to generate a quantum computing model to represent an electronic design automation (EDA) process for a circuit design.
Fedor G. Pikus, Shashank Jaiswal
Filed: 19 Nov 19
Utility
Layout-Friendly Test Pattern Decompressor
20 May 21
A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.
Yu Huang, Janusz Rajski, Mark A. Kassab, Nilanjan Mukherjee, Jeffrey Mayer
Filed: 28 Oct 20
Utility
Diagnostic Resolution Enhancement with Reversible Scan Chains
20 May 21
This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit.
Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
Filed: 26 Aug 20
Utility
CorrectedSystem for Processing Messages of Data Stream
22 Apr 21
A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.
Kari Vierimaa
Filed: 9 Jan 20
Utility
Genealogy Driven Ic Layout Generator and Classification Method
4 Mar 21
Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size.
Mohamed-Nabil Sabry, Kareem Madkour, Sherif Ahmed Abdel-Wahab Hammouda
Filed: 26 Aug 19
Utility
Memory System Query with Expanding Request
4 Mar 21
This application discloses a server configured to receive an expanding memory access request for nested data stored in a memory system having multiple relational tables.
Caleb Bauermeister, Eric E. Thompson, Darcy J. McCallum
Filed: 30 Aug 19
Utility
Templated Form Generation from Meta Model Based Rules with Concurrent Editing
4 Mar 21
This application discloses a computing system implementing a management system to generate a presentation populated with a portion of a meta model in response to a meta model access request for a first client device.
Christopher Schmitz, Eric E. Thompson, Darcy J. McCallum
Filed: 30 Aug 19
Utility
Edge-Based Camera for Characterizing Semiconductor Layout Designs
4 Mar 21
System and methods for an edge-based camera are disclosed.
Hazem Hegazy, Ahmed Hamed-Fatehy, Omar Elsewefy
Filed: 30 Aug 19
Utility
Voltage and Temperature Adaptive Memory Leakage Reduction Bias Circuit
4 Mar 21
This application discloses a memory device to retain stored data when receiving a voltage supply having at least a retention voltage level.
Kwan Him Lam
Filed: 28 Aug 19
Utility
Audio Data Augmentation for Machine Learning Object Classification
4 Mar 21
This application discloses a computing system to receive audio data corresponding to sounds emitted by objects capable of being identified in an environment.
Nizar Sallem, Ohad Barak
Filed: 29 Aug 19
Utility
Reversible Multi-Bit Scan Cell-based Scan Chains For Improving Chain Diagnostic Resolution
4 Feb 21
A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry.
Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
Filed: 20 Jul 20
Utility
Flexible Isometric Decompressor Architecture for Test Compression
21 Jan 21
A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry.
Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
Filed: 21 Mar 19
Utility
Deterministic Test Pattern Generation for Designs with Timing Exceptions
30 Dec 20
Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA).
Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
Filed: 21 Aug 19