51 patents
Page 2 of 3
Utility
Systems and Methods for Photolithographic Design
9 Dec 20
A method of identifying elements in a design layout having multiple levels of hierarchical cells, each cell having one or more geometric elements, may include selecting a cell from a list of candidate cells for a level of a hierarchy; applying a local rule to the selected cell; identifying each selected cell that includes a geometric element that passes the local rule; building a list of candidate cells for a next-higher level of the hierarchy according to the identified cells; repeating the selecting, identifying, and building operations for each higher level of the hierarchy; and when a highest level of the hierarchy has been processed, returning and storing the list of candidate cells as the global solution for the applied local rule.
Fedor G. Pikus
Filed: 25 Aug 20
Utility
Low Pin Count Reversible Scan Architecture
28 Oct 20
A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal.
Wu-Tung Cheng, Yu Huang
Filed: 22 Apr 20
Utility
Optimized Scan Chain Diagnostic Pattern Generation for Reversible Scan Architecture
21 Oct 20
A system and method for performing scan chain testing is disclosed.
Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma
Filed: 22 Aug 19
Utility
Identification of Key Errors In a System Having a Large Number of Error Events
14 Oct 20
A report of results of validating a circuit can simplify a large number of error events, that can be generated when designing electrical circuits using computer aided design tools, by first filtering the large number of error events according to a user defined filter criteria.
Michael Alam
Filed: 30 Mar 17
Utility
Scan Cell Architecture For Improving Test Coverage And Reducing Test Application Time
14 Oct 20
A scan cell comprises: a state element and selection and combination circuitry.
Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
Filed: 9 Apr 20
Utility
Circuit Validation for Circuits Comprising Multiple Possible Variants for Individual Components
23 Sep 20
Circuits may be designed using computer aided design tools and may comprise a plurality of different possible variants of individual components.
Michael Alam
Filed: 30 Mar 17
Utility
Machine Learning-based Adjustments In Volume Diagnosis Procedures for Determination of Root Cause Distributions
23 Sep 20
A computing system may include a model training engine configured to train a supervised learning model with a training set comprising training probability distributions computed for training dies through a local phase of a volume diagnosis procedure.
Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Yue Tian
Filed: 21 Mar 19
Utility
Machine Learning-based Parasitic Extraction Automation for Circuit Design and Verification
22 Jul 20
This application discloses a computing system implementing a parasitic extraction tool to generate parasitic netlists from tests cases including test layout models of integrated circuit structures.
Vasileios Kourkoulos, Rengjing Zhang, Joshua Adkins
Filed: 22 Aug 19
Utility
Hybrid Performance of Electronic Design Automation (Eda) Procedures with Delayed Acquisition of Remote Resources
8 Jul 20
A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine.
Robert A. Todd, Laurence W. Grodd, Jimmy J. Tomblin, Patrick D. Gibson
Filed: 3 Jan 19
Utility
System for Processing Messages of Data Stream
8 Jul 20
A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.
Kari Vierimaa
Filed: 8 Jan 20
Utility
Environmental Perception In Autonomous Driving Using Captured Audio
1 Jul 20
Amin Kashi, Glenn Perry, Ohad Barak, Nizar Sallem
Filed: 30 Dec 18
Utility
Chain Testing And Diagnosis Using Two-Dimensional Scan Architecture
27 May 20
A test pattern is shifted into scan chains in a circuit in a first direction.
Wu-Tung Cheng, Yu Huang
Filed: 25 Nov 19
Utility
Clock Gating And Scan Clock Generation For Circuit Test
6 May 20
A circuit comprises a clock gating device.
Jean-Francois Cote
Filed: 30 Oct 19
Utility
Local Clock Injection And Independent Capture For Circuit Test Of Multiple Cores In Clock Mesh Architecture
6 May 20
A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices.
Jean-Francois Cote
Filed: 30 Oct 19
Utility
Resource Utilization of Heterogeneous Compute Units In Electronic Design Automation
29 Apr 20
A system may include a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes compute units with differing computing capabilities.
Patrick D. Gibson, Robert A. Todd
Filed: 23 Oct 18
Utility
Interface Connectivity for Printed Circuit Board Schematic
1 Apr 20
This application discloses a computing system implementing a schematic capture tool to place and connect parts in a schematic design of a printed circuit board assembly.
Michal Paszek, Tomasz Zielski, Michal Ferdek, Pawel Cieslak, Marek Mossakowski
Filed: 27 Sep 18
Utility
Conductor Subdivision In Physical Integrated Circuit Layout for Parasitic Extraction
4 Mar 20
A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit.
Alexander Shurygin, James Falbo
Filed: 30 Aug 18
Utility
Hierarchical Expression Coverage Clustering for Design Verification
4 Mar 20
This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to detect a pattern in a subset of expressions within a circuit design describing an electronic device, generate a merged expression from the subset of the identified expressions corresponding to the detected pattern, generate a hierarchical representation of the expressions based, at least in part, on the merged expression, and generate an expression coverage presentation based on the hierarchical representation of the expressions and the coverage data.
Mennatallah Amer
Filed: 30 Aug 18
Utility
Layout Pattern Similarity Determination Based On Binary Turning Function Signatures
22 Jan 20
One or more binary turning function signatures for each of the layout patterns are determined.
Navin Srivastava, Hanzhong Xu, John Edward Hershberger
Filed: 17 Jul 19
Utility
Form Board Merge
8 Jan 20
This application discloses a computing system to merge a first form board design describing a configuration for use in manufacturing a first wire harness with a second form board design describing a configuration for use in manufacturing a second wire harness.
Alexander Sumner, Frank Hemmersbach, Mohamed El-Morsy, Adam Bedford, Vikas Maddukuri
Filed: 7 Jul 19