186 patents
Utility
Library cell modeling for transistor-level test pattern generation
25 Apr 23
This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns.
Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
Filed: 27 Aug 20
Utility
Isometric control data generation for test compression
23 Aug 22
The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains.
Yu Huang, Janusz Rajski, Sylwester Milewski
Filed: 21 Mar 19
Utility
Library Cell Modeling for Transistor-level Test Pattern Generation
3 Mar 22
This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns.
Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
Filed: 27 Aug 20
Utility
Suspect Resolution for Scan Chain Defect Diagnosis
3 Mar 22
This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting.
Grzegorz Mrugalski, Szczepan Urban, Jakub Janicki
Filed: 31 Aug 20
Utility
Optical proximity correction model verification
7 Dec 21
A computing system implementing an optical proximity correction model verification tool can determine parameters for design patterns associated with an integrated circuit described in a layer file, and determine differences between the design patterns and calibration patterns utilized to calibrate an optical proximity correction (OPC) model configured to predict a printed image on a substrate corresponding to a layout design for the integrated circuit by determining distances between the determined parameters for the design patterns and parameters for the calibration patterns.
Andrew Burbine, Germain Louis Fenger
Filed: 31 Aug 20
Utility
Deterministic Stellar Built-in Self Test
2 Dec 21
A system for testing a circuit comprises scan chains, a controller configured to generate a bit- inverting signal based on child test pattern information, and bit-inverting circuitry coupled to the controller and configured to invert bits of a parent test pattern associated with a plurality of shift clock cycles based on the bit-inverting signal to generate a child test pattern during a shift operation.
Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
Filed: 21 Mar 19
Utility
System and method for validation of photonics device layout designs
16 Nov 21
Systems and methods for validation of photonics device layout designs.
Nermeen Mohamed Hossam, Nadine Shehad
Filed: 17 Aug 20
Utility
Reversible multi-bit scan cell-based scan chains for improving chain diagnostic resolution
26 Oct 21
A circuit comprises a scan chain comprising one or more multi-bit flip-flops, a plurality of multiplexers, and new scan enable signal generation circuitry.
Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
Filed: 20 Jul 20
Utility
Flexible isometric decompressor architecture for test compression
19 Oct 21
A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry.
Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
Filed: 21 Mar 19
Utility
Self-diagnosis of faults in an autonomous driving system
12 Oct 21
This application discloses a computing system to self-diagnosis of faults for an assisted or automated driving system of a vehicle.
Ljubo Mercep, Matthias Pollach
Filed: 31 Jan 18
Utility
Virtual Ethernet mutable port group transactor
12 Oct 21
Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping.
Georges Antoun Elias Ghattas, Mohamed Ahmed Mostafa Shaaban, Robert John Bloor
Filed: 12 May 17
Utility
Multi-objective calibrations of lithography models
21 Sep 21
A system may include a model calibration engine configured to determine a candidate lithography model set from which to calibrate a lithography model according to multiple objectives, including by initializing a population of parent candidate models, generating child candidate models, merging the parent and child candidate models into a merged population, classifying the candidate models of the merged population into tiers of non-dominated fronts according to respective objective functions for the multiple objectives, determining a subset of the merged population based on the classified tiers, and identifying, as the candidate lithography model set, a Pareto-optimal front of the subset of the merged population determined based on the classified tiers.
Huikan Liu
Filed: 9 Jan 20
Utility
Reduce/broadcast computation-enabled switching elements in an emulation network
7 Sep 21
Each reconfigurable hardware modeling circuit of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device comprises: a model computation subsystem configurable either to model elements of a circuit design, or to serve as a testbench element, or both, and a network subsystem comprising: network circuitry and signal reduction circuitry, the signal reduction circuitry configurable to perform a signal reduction function, the signal reduction function combining a plurality of status signals into a single status signal, the plurality of status signals comprising status signals received from one or more reconfigurable hardware modeling circuits in the plurality of reconfigurable hardware modeling circuits.
Charles W Selvidge, Jean-Marc Brault, Jean-Paul Clavequin, Laurent Vuillemin
Filed: 25 Jun 20
Utility
Hotspot detection based on litho-aware machine learning
7 Sep 21
Aspects of the disclosed technology relate to techniques of hotspot detection.
Jea Woo Park, Juan Andres Torres Robles
Filed: 19 Sep 18
Utility
Diagnostic resolution enhancement with reversible scan chains
31 Aug 21
This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit.
Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
Filed: 26 Aug 20
Utility
Packet data protocol
17 Aug 21
A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.
Andrew Brian Thomas Hopkins, Iain Craig Robertson
Filed: 16 May 19
Utility
Chain testing and diagnosis using two-dimensional scan architecture
17 Aug 21
A test pattern is shifted into scan chains in a circuit in a first direction.
Wu-Tung Cheng, Yu Huang
Filed: 26 Nov 19
Utility
Machine Learning-based Classification In Parasitic Extraction Automation for Circuit Design and Verification
12 Aug 21
This application discloses a computing system implementing a parasitic extraction tool to generate a parasitic model from physical design layout of an integrated circuit.
Vasileios Kourkoulos, Lin Du, Renbo Chen
Filed: 12 Feb 20
Utility
Variable address length communication protocol
10 Aug 21
A communication unit and discoverable unit communicate according to a protocol in which unit addresses are not of a predetermined length.
Iain Robertson, Callum Stewart
Filed: 2 Jul 19
Utility
Clock gating and scan clock generation for circuit test
10 Aug 21
A circuit comprises a clock gating device.
Jean-Francois Cote
Filed: 31 Oct 19