186 patents
Page 2 of 10
Utility
Low pin count reversible scan architecture
27 Jul 21
A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal.
Wu-Tung Cheng, Yu Huang
Filed: 23 Apr 20
Utility
Event-driven region of interest management
20 Jul 21
This application discloses a computing system to implement event-driven region of interest management in an assisted or automated driving system of a vehicle.
Rainer Oder, Andreas Erich Geiger, Ljubo Mercep, Matthias Pollach
Filed: 6 Oct 16
Utility
Multi-objective Calibrations of Lithography Models
15 Jul 21
A system may include a model calibration engine configured to determine a candidate lithography model set from which to calibrate a lithography model according to multiple objectives, including by initializing a population of parent candidate models, generating child candidate models, merging the parent and child candidate models into a merged population, classifying the candidate models of the merged population into tiers of non-dominated fronts according to respective objective functions for the multiple objectives, determining a subset of the merged population based on the classified tiers, and identifying, as the candidate lithography model set, a Pareto-optimal front of the subset of the merged population determined based on the classified tiers.
Huikan Liu
Filed: 9 Jan 20
Utility
Method and system for calculating probability of success or failure for a lithographic process due to stochastic variations of the lithographic process
13 Jul 21
A method and system for calculating probability of success or failure for a lithographic process due to stochastic variations of the lithographic process are disclosed.
Gurdaman Khaira, Germain Louis Fenger, Azat Latypov, John L. Sturtevant, Yuri Granik
Filed: 20 Aug 19
Utility
Local clock injection and independent capture for circuit test of multiple cores in clock mesh architecture
22 Jun 21
A circuit comprises a burst clock control and gating device configured to generate a modified clock signal in a test mode by allowing a preset number of clock pulses of a clock signal to go through during each clock cycle of a reference clock signal, and a plurality of clock gating devices.
Jean-Francois Cote
Filed: 31 Oct 19
Utility
Optimized scan chain diagnostic pattern generation for reversible scan architecture
22 Jun 21
A system and method for performing scan chain testing is disclosed.
Yu Huang, Szczepan Urban, Wu-Tung Cheng, Manish Sharma
Filed: 23 Aug 19
Utility
Diagnosis resolution prediction
22 Jun 21
This application discloses a computing system implementing an automatic test pattern generation tool to generate test patterns to apply to scan chains in an integrated circuit.
Huaxing Tang, Jakub Janicki
Filed: 31 Aug 20
Utility
Parallel fault simulator with back propagation enhancement
15 Jun 21
This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector.
Sanjay Pillay, Arun Kumar Gogineni, Srikanth Rengarajan
Filed: 3 Dec 18
Utility
Error-Correcting Code-Assisted Memory Repair
10 Jun 21
A memory-testing circuit configured to perform a test of a memory comprising error-correcting code circuitry comprises repair circuitry configured to allocate a spare row or row block in the memory for a defective row or row block in the memory, a defective row or row block being a row or row block in which a memory word has a number of error bits greater than a preset number, wherein the test of the memory comprises: disabling the error-correcting code circuitry, performing a pre-repair operation, the pre-repair operation comprising: determining whether the memory has one or more defective rows or row blocks, and allocating one or more spare rows or row blocks for the one or more defective rows or row blocks if the one or more spare rows or row blocks are available, and performing a post-repair operation on the repaired memory.
Benoit Nadeau-Dostie
Filed: 9 Dec 20
Utility
Reconfiguring monitoring circuitry
1 Jun 21
A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip.
Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
Filed: 30 Jul 19
Utility
Puzzle-based pattern analysis and classification
1 Jun 21
Methods and apparatus for pattern matching and classification are disclosed.
Jia-Tze Huang, Jonathan James Muirhead
Filed: 11 Dec 18
Utility
System for processing messages of data stream
1 Jun 21
A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.
Kari Vierimaa
Filed: 9 Jan 20
Utility
Optical proximity correction modeling with density-based gauge weighting
1 Jun 21
This application discloses a computing system implementing an optical proximity correction model calibration tool to determine parameters for gauges describing features of an integrated circuit.
Germain Louis Fenger, Andrew Burbine, Christopher Clifford
Filed: 19 Aug 20
Utility
Trajectory-Optimized Test Pattern Generation for Built-In Self-Test
27 May 21
A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.
Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
Filed: 17 Nov 20
Utility
Concolic equivalence checking
25 May 21
This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values.
Pritam Roy, Sagar Chaki, Pankaj Chauhan
Filed: 24 Mar 20
Utility
Form board merge
25 May 21
This application discloses a computing system to merge a first form board design describing a configuration for use in manufacturing a first wire harness with a second form board design describing a configuration for use in manufacturing a second wire harness.
Alexander Sumner, Frank Hemmersbach, Mohamed El-Morsy, Adam Bedford, Vikas Maddukuri
Filed: 8 Jul 19
Utility
Edge-based camera for characterizing semiconductor layout designs
25 May 21
System and methods for an edge-based camera are disclosed.
Hazem Hegazy, Ahmed Hamed Fathi Hamed, Omar Elsewefy
Filed: 30 Aug 19
Utility
Adaptive Penalty Term Determinations In Applications of Quantum Computing to Electronic Design Automation Processes
20 May 21
A system may include a quantum model engine configured to generate a quantum computing model to represent an electronic design automation (EDA) process for a circuit design.
Fedor G. Pikus, Shashank Jaiswal
Filed: 19 Nov 19
Utility
Layout-Friendly Test Pattern Decompressor
20 May 21
A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.
Yu Huang, Janusz Rajski, Mark A. Kassab, Nilanjan Mukherjee, Jeffrey Mayer
Filed: 28 Oct 20
Utility
Diagnostic Resolution Enhancement with Reversible Scan Chains
20 May 21
This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit.
Wu-Tung Cheng, Szczepan Urban, Jakub Janicki, Manish Sharma, Yu Huang
Filed: 26 Aug 20