186 patents
Page 3 of 10
Utility
Prediction of test pattern counts for scan configuration determination
18 May 21
One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers.
Yu Huang, Janusz Rajski, Mark A. Kassab, Wu-Tung Cheng
Filed: 13 Apr 20
Utility
System and method for layout analysis using point of interest patterns and properties
11 May 21
Systems and methods for layout analysis using unit cell properties.
Sherif Hany Riad Mohammed Mousa, Jea Woo Park, Michael White
Filed: 3 Aug 20
Utility
Subtractive design for heat sink improvement
11 May 21
Aspects of the disclosed technology relate to techniques of improving heat sink designs based on systematic mass removal.
Robin Bornoff, John Richard Wilson, John Parry
Filed: 27 Sep 16
Utility
Environmental perception in autonomous driving using captured audio
4 May 21
This application discloses sensors to capture audio measurement in an environment around a vehicle and a computing system to classify audio measurements captured with one or more sensors mounted to a vehicle, wherein the classified audio measurements identify to a type of object in an environment around the vehicle, and fuse the classified audio measurements with measurements captured by at least one different type of sensor to detect the object in the environment around the vehicle, wherein a control system for the vehicle is configured to control operation of the vehicle based, at least in part, on the detected object.
Amin Kashi, Glenn Perry, Ohad Barak, Nizar Sallem
Filed: 31 Dec 18
Utility
Test generation using testability-based guidance
4 May 21
Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern.
Sylwester Milewski, Janusz Rajski, Yu Huang
Filed: 21 Mar 19
Utility
CorrectedSystem for Processing Messages of Data Stream
22 Apr 21
A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.
Kari Vierimaa
Filed: 9 Jan 20
Utility
Performance profiling for a multithreaded processor
13 Apr 21
An apparatus comprising: a processing unit configured to execute a plurality of threads; a profiling unit configured to: profile the operation of the processing unit over a time period to generate an activity profile indicating when each of the plurality of threads is executed by the processing unit over the time period; analyse the generated activity profile to determine whether a signature of the processing unit's thread execution for the time period matches a signature indicating a baseline of thread execution for the processing unit; output an alert signal if the signature of the processing unit's thread execution for the time period does not match the signature indicating a baseline of thread execution for the processing unit.
Gajinder Singh Panesar
Filed: 10 Apr 19
Utility
Deterministic test pattern generation for designs with timing exceptions
13 Apr 21
Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA).
Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
Filed: 22 Aug 19
Utility
Scan cell architecture for improving test coverage and reducing test application time
30 Mar 21
A scan cell comprises: a state element and selection and combination circuitry.
Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
Filed: 10 Apr 20
Utility
Test scheduling and test access in test compression environment
23 Mar 21
Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment.
Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
Filed: 16 Mar 11
Utility
Genealogy Driven Ic Layout Generator and Classification Method
4 Mar 21
Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size.
Mohamed-Nabil Sabry, Kareem Madkour, Sherif Ahmed Abdel-Wahab Hammouda
Filed: 26 Aug 19
Utility
Memory System Query with Expanding Request
4 Mar 21
This application discloses a server configured to receive an expanding memory access request for nested data stored in a memory system having multiple relational tables.
Caleb Bauermeister, Eric E. Thompson, Darcy J. McCallum
Filed: 30 Aug 19
Utility
Templated Form Generation from Meta Model Based Rules with Concurrent Editing
4 Mar 21
This application discloses a computing system implementing a management system to generate a presentation populated with a portion of a meta model in response to a meta model access request for a first client device.
Christopher Schmitz, Eric E. Thompson, Darcy J. McCallum
Filed: 30 Aug 19
Utility
Edge-Based Camera for Characterizing Semiconductor Layout Designs
4 Mar 21
System and methods for an edge-based camera are disclosed.
Hazem Hegazy, Ahmed Hamed-Fatehy, Omar Elsewefy
Filed: 30 Aug 19
Utility
Voltage and Temperature Adaptive Memory Leakage Reduction Bias Circuit
4 Mar 21
This application discloses a memory device to retain stored data when receiving a voltage supply having at least a retention voltage level.
Kwan Him Lam
Filed: 28 Aug 19
Utility
Audio Data Augmentation for Machine Learning Object Classification
4 Mar 21
This application discloses a computing system to receive audio data corresponding to sounds emitted by objects capable of being identified in an environment.
Nizar Sallem, Ohad Barak
Filed: 29 Aug 19
Utility
Voltage and temperature adaptive memory leakage reduction bias circuit
2 Mar 21
This application discloses a memory device to retain stored data when receiving a voltage supply having at least a retention voltage level.
Kwan Him Lam
Filed: 28 Aug 19
Utility
Verification of photonic integrated circuits
23 Feb 21
Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs.
Ruping Cao, John G. Ferguson, John D. Cayo, Alexandre Arriordaz
Filed: 12 Dec 18
Utility
Circuit validation for circuits comprising multiple possible variants for individual components
23 Feb 21
Circuits may be designed using computer aided design tools and may comprise a plurality of different possible variants of individual components.
Michael Alam
Filed: 31 Mar 17
Utility
Genealogy driven IC layout generator and classification method
16 Feb 21
Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size.
Mohamed-Nabil Sabry, Kareem Madkour, Sherif Ahmed Abdel-Wahab Hammouda
Filed: 26 Aug 19