134 patents
Utility
Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network
16 Jan 24
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Nhan Do, Mark Reiten
Filed: 4 Jan 21
Utility
Virtual ground non-volatile memory array
19 Dec 23
A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates.
Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
Filed: 21 Jun 22
Utility
Precise data tuning method and apparatus for analog neural memory in an artificial neural network
19 Dec 23
Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 27 Jul 22
Utility
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
19 Dec 23
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Verification of a weight stored in a non-volatile memory cell in a neural network following a programming operation
28 Nov 23
Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 16 Apr 21
Utility
Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
24 Oct 23
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Precision tuning of a page or word of non-volatile memory cells in an analog neural memory system
24 Oct 23
Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Vipin Tiwari, Nhan Do
Filed: 4 Jul 22
Utility
Hierarchical ROM encoder system for performing address fault detection in a memory system
24 Oct 23
Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system.
Xiaozhou Qian, Yaohua Zhu
Filed: 11 Feb 22
Utility
Split-gate flash memory cell with improved control gate capacitive coupling, and method of making same
24 Oct 23
A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate.
Leo Xing, Chunming Wang, Xian Liu, Nhan Do, Guo Xiang Song
Filed: 14 Jun 21
Utility
Output circuitry for non-volatile memory array in neural network
17 Oct 23
A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 22 Apr 21
Utility
Compensation for leakage in an array of analog neural memory cells in an artificial neural network
10 Oct 23
In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
Filed: 13 Jun 22
Utility
Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells
26 Sep 23
A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2.
Viktor Markov, Alexander Kotov
Filed: 22 Sep 21
Utility
Precise programming method and apparatus for analog neural memory in an artificial neural network
12 Sep 23
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 23 Jan 20
Utility
Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate
22 Aug 23
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.
Guo Xiang Song, Chunming Wang, Leo Xing, Xian Liu, Nhan Do
Filed: 4 Jun 21
Utility
Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network
15 Aug 23
Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 14 Dec 20
Utility
Programming analog neural memory cells in deep learning artificial neural network
15 Aug 23
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 2 May 22
Utility
Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps
16 May 23
A simplified method for forming a non-volatile memory cell using two polysilicon depositions.
Feng Zhou, Xian Liu, Chien-Sheng Su, Nhan Do, Chunming Wang
Filed: 15 Sep 20
Utility
Neural network classifier using array of three-gate non-volatile memory cells
9 May 23
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 9 Sep 21
Utility
Set-while-verify circuit and reset-while verify circuit for resistive random access memory cells
9 May 23
Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
Filed: 11 Mar 21
Utility
Precise data tuning method and apparatus for analog neural memory in an artificial neural network
25 Apr 23
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 25 Mar 20