157 patents
Utility
Programming of a Selected Non-volatile Memory Cell
16 Nov 23
In one example, a method comprises performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 27 Jul 23
Utility
Method of Screening Non-volatile Memory Cells
19 Oct 23
A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.
Viktor Markov, ALEXANDER KOTOV
Filed: 6 Jul 22
Utility
Artificial Neural Network Comprising a Three-dimensional Integrated Circuit
12 Oct 23
Numerous examples are disclosed of an artificial neural network comprising a three-dimensional integrated circuit.
Hieu Van Tran, Mark Reiten, Nhan Do
Filed: 23 Jun 22
Utility
Artificial Neural Network Comprising Reference Array for I-v Slope Configuration
12 Oct 23
Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array.
Hieu Van Tran, THUAN VU, STANLEY HONG, STEPHEN TRINH, STEVEN LEMKE, LOUISA SCHNEIDER, NHAN DO
Filed: 23 Jun 22
Utility
Vector-by-matrix-multiplication Array Utilizing Analog Inputs
12 Oct 23
Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Mark Reiten
Filed: 23 Jun 22
Utility
Vector-by-matrix-multiplication Array Utilizing Analog Outputs
12 Oct 23
Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs.
Hieu Van Tran, THUAN VU, STANLEY HONG, STEPHEN TRINH, MARK REITEN
Filed: 23 Jun 22
Utility
Calibration of Electrical Parameters In a Deep Learning Artificial Neural Network
28 Sep 23
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network.
Hieu Van Tran
Filed: 19 Apr 22
Utility
Method of Forming a Device with Planar Split Gate Non-volatile Memory Cells, Planar HV Devices, and Finfet Logic Devices on a Substrate
14 Sep 23
A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.
Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
Filed: 25 May 22
Utility
Method of Forming Memory Cells, High Voltage Devices and Logic Devices on a Semiconductor Substrate
14 Sep 23
A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
Filed: 7 Jun 22
Utility
Memory Device of Non-volatile Memory Cells
17 Aug 23
A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns.
Hieu Van Tran, NHAN DO, FARNOOD MERRIKH BAYAT, XINJIE GUO, DMITRI STRUKOV, VIPIN TIWARI, MARK REITEN
Filed: 28 Apr 23
Utility
Method of Forming a Semiconductor Device with Memory Cells, High Voltage Devices and Logic Devices on a Substrate Using a Dummy Area
17 Aug 23
A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material.
Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
Filed: 16 May 22
Utility
Method Of Scanning An Image Using Non-volatile Memory Array Neural Network Classifier
10 Aug 23
A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 24 Mar 23
Utility
Calibration of Electrical Parameters In a Deep Learning Artificial Neural Network
10 Aug 23
Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network.
Hieu Van Tran
Filed: 22 Apr 22
Utility
Artificial Neural Network Comprising an Analog Array and a Digital Array
3 Aug 23
Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 14 Apr 22
Utility
Method of Forming Pairs of Three-gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps
27 Jul 23
A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions.
Feng Zhou, XIAN LIU, CHIEN-SHENG SU, Nhan DO, CHUNMING WANG
Filed: 27 Mar 23
Utility
Output Circuitry for Non-volatile Memory Array In Neural Network
20 Jul 23
Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods.
Farnood Merrikh BAYAT, Xinjie GUO, Dmitri STRUKOV, Nhan DO, Hieu Van TRAN, Vipin TIWARI, Mark REITEN
Filed: 20 Mar 23
Utility
Summing Circuit for Neural Network
20 Jul 23
Numerous examples of summing circuits for a neural network are disclosed.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 20 Mar 23
Utility
Split Array Architecture for Analog Neural Memory In a Deep Learning Artificial Neural Network
20 Jul 23
Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 23 Mar 23
Utility
Neural Network Classifier Using Array of Three-gate Non-volatile Memory Cells
13 Jul 23
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 21 Mar 23
Utility
Verification of a Weight Stored In a Non-volatile Memory Cell In a Neural Network Following a Programming Operation
29 Jun 23
Numerous examples are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 10 Mar 23