157 patents
Page 2 of 8
Utility
Address Fault Detection In a Memory System
25 May 23
Various examples of memory systems comprising an address fault detection system are disclosed.
Hieu Van Tran
Filed: 28 Jan 22
Utility
Determination of a Bias Voltage to Apply to One or More Memory Cells In a Neural Network
18 May 23
Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed.
Hieu Van Tran
Filed: 26 Jan 22
Utility
Transceiver for Providing High Voltages for Erase or Program Operations In a Non-volatile Memory System
11 May 23
Numerous embodiments of a transceiver for providing high voltages for use during erase or program operations in a non-volatile memory system are disclosed.
Hieu Van Tran, Anh Ly, Kha Nguyen, Hien Pham, Duc Nguyen
Filed: 26 Jan 22
Utility
Adjustable Programming Circuit for Neural Network
20 Apr 23
Examples of programming circuits and methods are provided.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 14 Dec 22
Utility
Adjustable Programming Circuit for Neural Network
6 Apr 23
Examples of programming circuits and methods are disclosed.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly
Filed: 13 Dec 22
Utility
Method of Determining Defective Die Containing Non-volatile Memory Cells
30 Mar 23
A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RC1 for the memory cells and a first number N1 of the memory cells having the lowest read current RC1.
Yuri Tkachev, JINHO KIM, CYNTHIA FUNG, GILLES FESTES, BERNARD BERTELLO, PARVIZ GHAZAVI, BRUNO VILLARD, JEAN FRANCOIS THIERY, CATHERINE DECOBERT, SERGUEI JOURBA, FAN LUO, LATT TEE, NHAN DO
Filed: 14 Jan 22
Utility
Hybrid Memory System Configurable to Store Neural Memory Weight Data In Analog Form or Digital Form
23 Feb 23
Numerous embodiments of a hybrid memory system are disclosed.
Hieu Van Tran
Filed: 4 Nov 21
Utility
Input Circuitry for Analog Neural Memory In a Deep Learning Artificial Neural Network
16 Feb 23
Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.
Hieu Van Tran, KHA NGUYEN, THUAN VU, HIEN PHAM, STANLEY HONG, STEPHEN TRINH
Filed: 5 Nov 21
Utility
Output Circuitry for Analog Neural Memory In a Deep Learning Artificial Neural Network
16 Feb 23
Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.
Hieu Van Tran, Thuan Vu
Filed: 8 Nov 21
Utility
Input Function Circuit Block and Output Neuron Circuit Block Coupled to a Vector-by-matrix Multiplication Array In an Artificial Neural Network
2 Feb 23
Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 21 Sep 22
Utility
Read and Programming Decoding System for Analog Neural Memory
19 Jan 23
Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
Filed: 29 Jun 22
Utility
Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
22 Dec 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
Filed: 22 Aug 22
Utility
Testing Circuitry And Methods For Analog Neural Memory In Artificial Neural Network
15 Dec 22
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks.
Hieu Van TRAN, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Steven LEMKE, Nha NGUYEN, Vipin TIWARI, Nhan DO
Filed: 22 Aug 22
Utility
Compensation For Reference Transistors And Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network
8 Dec 22
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Method of Improving Read Current Stability In Analog Non-volatile Memory by Post-program Tuning for Memory Cells Exhibiting Random Telegraph Noise
8 Dec 22
A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current.
VIKTOR MARKOV, ALEXANDER KOTOV
Filed: 21 Sep 21
Utility
Method of Reducing Random Telegraph Noise In Non-volatile Memory by Grouping and Screening Memory Cells
8 Dec 22
A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2.
Viktor Markov, ALEXANDER KOTOV
Filed: 22 Sep 21
Utility
Precision Tuning for the Programming of Analog Neural Memory In a Deep Learning Artificial Neural Network
1 Dec 22
Numerous examples of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.
HIEU VAN TRAN, STEVEN LEMKE, VIPIN TIWARI, NHAN DO, MARK REITEN
Filed: 27 Jul 22
Utility
Compensation for Reference Transistors and Memory Cells In Analog Neuro Memory In Deep Learning Artificial Neural Network
1 Dec 22
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 10 Aug 22
Utility
Output Circuit for Analog Neural Memory In a Deep Learning Artificial Neural Network
24 Nov 22
Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Mark Reiten
Filed: 31 Aug 21
Utility
Split Array Architecture for Analog Neural Memory In a Deep Learning Artificial Neural Network
24 Nov 22
Numerous embodiments are disclosed for splitting an array of non-volatile memory cells in an analog neural memory in a deep learning artificial neural network into multiple parts.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 30 Aug 21