157 patents
Page 4 of 8
Utility
Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate With Silicide On Conductive Blocks
17 Feb 22
A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material.
Chunming Wang, JACK SUN, XIAN LIU, LEO XING, NHAN DO, ANDY YANG, GUO XIANG SONG
Filed: 25 Feb 21
Utility
Method Of Forming Split Gate Memory Cells With Thinner Tunnel Oxide
13 Jan 22
A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.
Jeng-Wei YANG, Man-Tang WU, Boolean FAN, Nhan DO
Filed: 18 Feb 21
Utility
Adaptive Bias Decoder for Analog Neural Memory Array In Artificial Neural Network
6 Jan 22
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Nhan Do, Mark Reiten
Filed: 4 Jan 21
Utility
Neural Network Classifier Using Array of Three-gate Non-volatile Memory Cells
30 Dec 21
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region.
Hieu Van Tran, Steven Lemke, Vipin Tiwari, Nhan Do, Mark Reiten
Filed: 9 Sep 21
Utility
Method of Improving Read Current Stability In Analog Non-volatile Memory by Program Adjustment for Memory Cells Exhibiting Random Telegraph Noise
30 Dec 21
A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate.
Viktor Markov, Alexander Kotov
Filed: 29 Jun 20
Utility
Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate
23 Dec 21
A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.
Jack Sun, Chunming Wang, Xian Liu, Andy Yang, Guo Xiang Song, Leo Xing, Nhan Do
Filed: 21 Dec 20
Utility
Method Of Forming Split Gate Memory Cells With Thinned Side Edge Tunnel Oxide
23 Dec 21
A memory device includes a semiconductor substrate with memory cell and logic regions.
Jinho Kim, Elizabeth Cuevas, Yuri Tkachev, Parviz Ghazavi, Bernard Bertello, Gilles Festes, Bruno Villard, Catherine Decobert, Nhan Do, Jean Francois Thiery
Filed: 23 Jun 20
Utility
Word Line and Control Gate Line Tandem Decoder for Analog Neural Memory In Deep Learning Artificial Neural Network
9 Dec 21
Various embodiments of tandem row decoders are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly
Filed: 25 Nov 20
Utility
Self-timed Sensing Architecture for a Non-volatile Memory System
25 Nov 21
A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed.
Massimiliano Frulio
Filed: 11 Nov 20
Utility
Analog Neural Memory Array In Artificial Neural Network Comprising Logical Cells and Improved Programming Mechanism
18 Nov 21
Numerous embodiments of analog neural memory arrays are disclosed.
HIEU VAN TRAN, STANLEY HONG, STEPHEN TRINH, THUAN VU, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
Filed: 28 Oct 20
Utility
Analog Neural Memory Array In Artificial Neural Network with Source Line Pulldown Mechanism
11 Nov 21
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Vipin Tiwari, Han Tran, Hien Pham
Filed: 5 Nov 20
Utility
Decoders for Analog Neural Memory In Deep Learning Artificial Neural Network
4 Nov 21
Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, STANLEY HONG, ANH LY, THUAN VU, HIEN PHAM, KHA NGUYEN, HAN TRAN
Filed: 6 Jul 21
Utility
Programmable Output Blocks for Analog Neural Memory In a Deep Learning Artificial Neural Network
28 Oct 21
Numerous embodiments are disclosed for programmable output blocks for use with a VMM array within an artificial neural network.
Hieu Van Tran
Filed: 5 Jul 21
Utility
Non-volatile Memory System Using Strap Cells In Source Line Pull Down Circuits
21 Oct 21
The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits.
Leo XING, Chunming WANG, Xian LIU, Nhan DO, Guangming LIN, Yaohua ZHU
Filed: 19 Oct 20
Utility
Finfet Split Gate Non-volatile Memory Cells with Enhanced Floating Gate to Floating Gate Capacitive Coupling
30 Sep 21
Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region.
Feng Zhou, Xian Liu, Steven Lemke, Hieu Van Tran, Nhan Do
Filed: 13 Oct 20
Utility
Precision Tuning of a Page or Word of Non-volatile Memory Cells and Associated High Voltage Circuits for an Analog Neural Memory Array In an Artificial Neural Network
23 Sep 21
Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed.
HIEU VAN TRAN, THUAN VU, STEPHEN TRINH, STANLEY HONG, ANH LY, STEVEN LEMKE, VIPIN TIWARI, NHAN DO
Filed: 17 Sep 20
Utility
Output Circuitry for Non-volatile Memory Array In Neural Network
16 Sep 21
A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed.
Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Nhan Do, Hieu Van Tran, Vipin Tiwari, Mark Reiten
Filed: 22 Apr 21
Utility
Analog Neural Memory Array In Artificial Neural Network with Substantially Constant Array Source Impedance with Adaptive Weight Mapping and Distributed Power
9 Sep 21
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan VU, Stephen TRINH, Stanley HONG, Anh LY, Vipin Tiwari
Filed: 6 Aug 20
Utility
Analog Neural Memory Array Storing Synapsis Weights In Differential Cell Pairs In Artificial Neural Network
9 Sep 21
Numerous embodiments of analog neural memory arrays are disclosed.
Hieu Van Tran, Thuan VU, STEPHEN TRINH, STANLEY HONG, ANH LY, VIPIN Tiwari
Filed: 6 Aug 20
Utility
Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices
2 Sep 21
A method of forming a device with a silicon substrate having upwardly extending first and second fins.
Feng Zhou, Xian Liu, JinHo Kim, Serguei Jourba, Catherine Decobert, Nhan Do
Filed: 27 Feb 20