540 patents
Page 8 of 27
Utility
Field Effect Transistors with Modified Access Regions
24 Nov 22
A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer.
Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
Filed: 20 May 21
Design
Power module
15 Nov 22
Brice McPherson, Alexander Lostetter
Filed: 5 Nov 20
Design
Power semiconductor package
15 Nov 22
Kuldeep Saxena
Filed: 11 Oct 21
Utility
Field effect transistor with at least partially recessed field plate
15 Nov 22
A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer.
Kyle Bothe, Jia Guo, Terry Alcorn, Fabian Radulescu, Scott Sheppard
Filed: 27 Oct 20
Utility
Multi-Cavity Package Having Single Metal Flange
3 Nov 22
A multi-cavity package includes a single metal flange having first and second opposing main surfaces.
Saurabh Goel, Alexander Komposch, Cynthia Blair, Cristian Gozzi
Filed: 19 Jul 22
Utility
High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices
3 Nov 22
A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices.
Matthew FEURTADO, Brice MCPHERSON, Daniel MARTIN, Alexander LOSTETTER
Filed: 7 Jul 22
Utility
High reliability semiconductor devices and methods of fabricating the same
1 Nov 22
A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die.
Sung Chul Joo, Alexander Komposch, Brian William Condie, Benjamin Law, Jae Hyung Jeremiah Park
Filed: 24 May 19
Utility
Vertical semiconductor device with improved ruggedness
1 Nov 22
A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.
Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Kijeong Han, Edward Robert Van Brunt
Filed: 24 Jul 20
Utility
Gallium Nitride High-electron Mobility Transistors with P-type Layers and Process for Making the Same
27 Oct 22
A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer.
Saptharishi SRIRAM
Filed: 7 Jul 22
Utility
Structures for reducing electron concentration and process for reducing electron concentration
18 Oct 22
A device includes a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer, a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; and a drain electrically coupled to the barrier layer.
Jia Guo, Scott Sheppard, Saptharishi Sriram
Filed: 18 Mar 19
Utility
Field Effect Transistor with Stacked Unit Subcell Structure
13 Oct 22
A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction.
Kyle Bothe, Jia Guo, Yueying Liu, Jeremy Fisher, Scott T. Sheppard
Filed: 24 Jun 22
Utility
RF Amplifier Devices and Methods of Manufacturing Including Modularized Designs with Flip Chip Interconnections
6 Oct 22
A transistor amplifier includes a die comprising a gate terminal, a drain terminal, and a source terminal, a circuitry module on the transistor die and electrically coupled to the gate terminal, the drain terminal, and/or the source terminal, and one or more passive electrical components on a first surface of the circuitry module.
Basim Noori, Marvin Marbell, Scott Sheppard, Kwangmo Chris Lim, Alexander Komposch, Qianli Mu, Michael DeVita
Filed: 24 Jun 22
Utility
High Power Transistor with Interior-fed Fingers
22 Sep 22
A transistor device includes a gate finger and a drain finger extending on a semiconductor structure, a gate bond pad coupled to the gate finger, and a drain bond pad coupled to the drain finger.
Frank Trang, Zulhazmi Mokhti, Haedong Jang
Filed: 7 Jun 22
Utility
Field Effect Transistor with Multiple Stepped Field Plate
22 Sep 22
A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer.
Jia Guo, Kyle Bothe, Scott Sheppard
Filed: 7 Jun 22
Utility
Trench Bottom Shielding Methods and Approaches for Trenched Semiconductor Device Structures
15 Sep 22
Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device.
Woongsun Kim, Daniel J. Lichtenwalner, Naeem Islam, Sei-Hyung Ryu
Filed: 3 Jun 22
Utility
High power multilayer module having low inductance and fast switching for paralleling power devices
13 Sep 22
A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices.
Matthew Feurtado, Brice McPherson, Daniel Martin, Alexander Lostetter
Filed: 15 Jan 21
Utility
Multi-cavity package having single metal flange
6 Sep 22
A multi-cavity package includes a single metal flange having first and second opposing main surfaces.
Saurabh Goel, Alexander Komposch, Cynthia Blair, Cristian Gozzi
Filed: 1 Oct 19
Utility
Gallium nitride high-electron mobility transistors with p-type layers and process for making the same
30 Aug 22
A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer.
Saptharishi Sriram
Filed: 24 Jun 16
Utility
Drain and/or gate interconnect and finger structure
23 Aug 22
Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a gate finger extending on the semiconductor structure in a first direction, and a gate interconnect extending in the first direction and configured to be coupled to a gate signal at an interior position of the gate interconnect, where the gate interconnect is connected to the gate finger at a position offset from the interior position of the gate interconnect.
Frank Trang, Zulhazmi Mokhti, Haedong Jang
Filed: 20 Aug 20
Utility
Integrated circuit having die attach materials with channels and process of implementing the same
23 Aug 22
A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material.
Mitch Flowers, Erwin Cohen, Alexander Komposch
Filed: 7 May 20