540 patents
Page 6 of 27
Utility
Power semiconductor devices including a trenched gate and methods of forming such devices
2 May 23
Semiconductor devices and methods of forming the devices are provided.
Daniel Lichtenwalner, Sei-Hyung Ryu, Naeem Islam, Woongsun Kim, Matt N. McCain, Joe McPherson
Filed: 27 Oct 20
Utility
Transistor with Ohmic Contacts
27 Apr 23
A transistor includes a semiconductor layer and a channel region.
Kyle Bothe, Evan Jones
Filed: 22 Oct 21
Utility
Methods of Forming Packaged Semiconductor Devices and Leadframes for Semiconductor Device Packages
20 Apr 23
A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.
Soon Lee Liew, Eng Wah Woo, Alexander Komposch
Filed: 18 Oct 21
Utility
Multiple Silicide Process for Separately Forming N-type and P-type Ohmic Contacts and Related Devices
20 Apr 23
A power semiconductor device includes a semiconductor layer structure comprising a wide bandgap semiconductor material.
Thomas E. Harrington, III, Shadi Sabri
Filed: 20 Oct 21
Utility
Transistor Device Structure with Angled Wire Bonds
20 Apr 23
A transistor device includes a substrate, a gate contact pad on the substrate, and a transistor die on the substrate adjacent the gate contact pad.
Kyoung-Keun Lee, Tim McManus
Filed: 18 Oct 21
Utility
Power Semiconductor Devices Including Multiple Gate Bond Pads
20 Apr 23
Power semiconductor devices comprise a silicon carbide based semiconductor layer structure including an active region defined therein and a gate bond pad that is on the semiconductor layer structure and vertically overlaps the active region.
Thomas E. Harrington, III, Daniel Jenner Lichtenwalner, Edward Robert Van Brunt
Filed: 4 Apr 22
Utility
Die-to-die isolation structures for packaged transistor devices
4 Apr 23
A transistor amplifier package includes a base, one or more transistor dies on the base, first and second leads coupled to the one or more transistor dies and defining respective radio frequency (RF) signal paths, and an isolation structure on the base between the respective RF signal paths.
Lei Zhao, Fabian Radulescu
Filed: 30 Jul 20
Utility
Compensation of trapping in field effect transistors
4 Apr 23
A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor.
Young-Youl Song, Zulhazmi A. Mokhti, John Wood, Qianli Mu, Jeremy Fisher
Filed: 5 Aug 21
Utility
High electron mobility transistors and power amplifiers including said transistors having improved performance and reliability
28 Mar 23
A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.
Kyle Bothe, Evan Jones, Dan Namishia, Chris Hardiman, Fabian Radulescu, Terry Alcorn, Scott Sheppard, Bruce Schmukler
Filed: 19 Feb 21
Utility
Vertical Power Devices Fabricated Using Implanted Methods
23 Mar 23
A precursor for a vertical semiconductor device is provided with a substrate, a drift region over the substrate, and an upper precursor region over the drift region.
Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Arman Ur Rashid
Filed: 22 Sep 21
Utility
Gate trench power semiconductor devices having improved deep shield connection patterns
21 Mar 23
A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall.
Naeem Islam, Woongsun Kim, Daniel J. Lichtenwalner, Sei-Hyung Ryu
Filed: 28 Oct 20
Utility
Semiconductor Device Incorporating a Substrate Recess
16 Mar 23
A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure.
Evan Jones, Saptha Sriram, Kyle Bothe
Filed: 16 Sep 21
Utility
Metal Pillar Connection Topologies for Heterogeneous Packaging
9 Mar 23
A radio frequency (“RF”) transistor amplifier die includes a semiconductor layer structure having a plurality of transistor cells, and an insulating layer on a surface of the semiconductor layer structure.
Fabian Radulescu, Basim Noori, Scott Sheppard, Kwangmo Chris Lim
Filed: 3 Sep 21
Utility
Edge termination structures for semiconductor devices
7 Mar 23
Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed.
Edward Robert Van Brunt, Thomas E. Harrington, III
Filed: 24 Sep 20
Utility
Monolithic microwave integrated circuits having both enhancement-mode and depletion mode transistors
28 Feb 23
A gallium nitride based monolithic microwave integrated circuit includes a substrate, a channel layer on the substrate and a barrier layer on the channel layer.
Saptharishi Sriram, Jennifer Qingzhu Gao, Jeremy Fisher, Scott Sheppard
Filed: 4 Dec 20
Utility
Semiconductor die with improved ruggedness
21 Feb 23
A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate.
Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
Filed: 29 Oct 20
Utility
Radio frequency transistor amplifiers having leadframes with integrated shunt inductors and/or direct current voltage source inputs
21 Feb 23
A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die.
Madhu Chidurala, Richard Wilson, Haedong Jang, Simon Ward
Filed: 24 Jun 20
Utility
Device design for short-circuitry protection circuitry within transistors
14 Feb 23
A transistor semiconductor die includes a first current terminal, a second current terminal, and a control terminal.
James Richmond, Edward Robert Van Brunt, Philipp Steinmann
Filed: 21 Jun 19
Utility
Radio frequency (RF) transistor amplifier packages with improved isolation and lead configurations
14 Feb 23
A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount.
Alexander Komposch, Qianli Mu, Kun Wang, Eng Wah Woo
Filed: 26 Jun 20
Utility
Compensation of Trapping In Field Effect Transistors
9 Feb 23
A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor.
Young-Youl Song, Zulhazmi A. Mokhti, John Wood, Qianli Mu, Jeremy Fisher
Filed: 5 Aug 21