540 patents
Page 4 of 27
Utility
Drain and/or gate interconnect and finger structure
12 Sep 23
Pursuant to some embodiments of the present invention, transistor devices are provided that include a semiconductor structure, a drain finger extending on the semiconductor structure in a first direction, and a drain interconnect extending in the first direction and configured to be coupled to a drain signal at an interior position of the drain interconnect, where the drain interconnect is connected to the drain finger at a position offset from the interior position of the drain interconnect.
Frank Trang, Zulhazmi Mokhti, Haedong Jang
Filed: 7 Jun 22
Utility
Field effect transistor with source-connected field plate
5 Sep 23
A transistor device includes a semiconductor layer, source and drain contacts on the semiconductor layer, a gate contact on the semiconductor layer between the source and drain contacts, and a field plate over the semiconductor layer between the gate contact and the drain contact.
Kyle Bothe, Jeremy Fisher, Matt King, Jia Guo, Qianli Mu, Scott Sheppard
Filed: 20 May 21
Utility
Power module
22 Aug 23
The present disclosure relates to a power module comprising a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies.
Brice McPherson
Filed: 24 Jul 20
Utility
Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same
22 Aug 23
A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.
Fabian Radulescu
Filed: 17 Feb 20
Utility
Semiconductor Packages with Increased Power Handling
17 Aug 23
Semiconductor packages and, more particularly, semiconductor packages with increased power handling capabilities are disclosed.
Geza Dezsi, Devarajan Balaraman, Brice McPherson
Filed: 11 Feb 22
Utility
Radio Frequency Transistor Amplifiers Having Self-aligned Double Implanted Source/drain Regions for Improved On-resistance Performance and Related Methods
17 Aug 23
A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer.
Kyle Bothe, Chloe Hawes, Jennifer Gao, Scott Sheppard
Filed: 11 Feb 22
Utility
Semiconductor Power Devices Having Multiple Gate Trenches and Methods of Forming Such Devices
17 Aug 23
A semiconductor device includes a semiconductor layer structure and a gate formed in a gate trench in the semiconductor layer structure.
Woongsun Kim, Daniel Jenner Lichtenwalner, Sei-Hyung Ryu, Naeem Islam
Filed: 19 Apr 23
Utility
Semiconductor Die Including a Metal Stack
10 Aug 23
A semiconductor die includes a silicon carbide (SiC) substrate and a metal stack.
Alexander Komposch, Arthur Fong-Yuen Pun, Scott T. Sheppard, Kevin Shawne Schneider
Filed: 4 Feb 22
Utility
Bypassed Gate Transistors Having Improved Stability
10 Aug 23
A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other.
Jeremy Fisher, Scott Sheppard, Khaled Fayed, Simon Wood
Filed: 15 Mar 23
Utility
Power module
8 Aug 23
The present disclosure describes a power module having a substrate, first and second pluralities of vertical power devices, and first and second terminal assemblies.
Brice McPherson, Brandon Passmore, Roberto M. Schupbach, Jennifer Stabach-Smith
Filed: 23 Apr 21
Utility
Methods of forming semiconductor power devices having graded lateral doping
8 Aug 23
A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer.
Philipp Steinmann, Edward Van Brunt, Jae Hyung Park, Vaishno Dasika
Filed: 11 Feb 22
Utility
Silicon Carbide Wafers with Relaxed Positive Bow and Related Methods
3 Aug 23
Silicon carbide (SiC) wafers and related methods are disclosed that include intentional or imposed wafer shapes that are configured to reduce manufacturing problems associated with deformation, bowing, or sagging of such wafers due to gravitational forces or from preexisting crystal stress.
Simon Bubel, Matthew Donofrio, John Edmond, Ian Currier
Filed: 7 Apr 23
Utility
Wide Bandgap Unipolar/bipolar Transistor
3 Aug 23
A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and first and second contacts on the semiconductor layer structure.
Thomas E. Harrington, III
Filed: 1 Feb 22
Utility
Wirebond-constructed inductors
1 Aug 23
Fabrication of a bondwire inductor between connection pads of a semiconductor package using a wire bonding process is disclosed herein.
Kenneth P. Brewer, Warren Brakensiek
Filed: 30 Apr 20
Utility
Power Semiconductor Devices Including a Trenched Gate and Methods of Forming Such Devices
20 Jul 23
Semiconductor devices and methods of forming the devices are provided.
Daniel Lichtenwalner, Sei-Hyung Ryu, Naeem Islam, Woongsun Kim, Matt N. McCain, Joe McPherson
Filed: 24 Mar 23
Utility
Limiting Failures Caused by Dendrite Growth on Semiconductor Chips
6 Jul 23
A semiconductor chip comprises a substrate, a die attach material, and a die.
Dan Namishia, Mitch Flowers, Eng Wah Woo, Erwin Cohen
Filed: 3 Jan 22
Utility
High power multilayer module having low inductance and fast switching for paralleling power devices
4 Jul 23
A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices.
Matthew Feurtado, Brice McPherson, Daniel Martin, Alexander Lostetter
Filed: 7 Jul 22
Utility
Device Having a Coupled Interstage Transformer and Process Implementing the Same
29 Jun 23
A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects.
Marvin MARBELL
Filed: 23 Dec 21
Utility
Gate Trench Power Semiconductor Devices Having Improved Deep Shield Connection Patterns
29 Jun 23
A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall.
Naeem Islam, Woongsun Kim, Daniel J. Lichtenwalner, Sei-Hyung Ryu
Filed: 15 Feb 23
Utility
Integrated passive device (IPD) components and a package and processes implementing the same
27 Jun 23
An RF transistor package includes a metal submount; a transistor die mounted to the metal submount; and a surface mount IPD component mounted to the metal submount.
Marvin Marbell, Arthur Pun, Jeremy Fisher, Ulf Andre, Alexander Komposch
Filed: 7 May 21