696 patents
Utility
High-Performance, High-Capacity Memory Systems and Modules
18 Jan 24
Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity.
Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Craig E. Hampel, Scott C. Best, John Yan
Filed: 4 Aug 23
Utility
Folded Memory Modules
18 Jan 24
A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories.
Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
Filed: 20 Jul 23
Utility
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18 Jan 24
In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval.
Torsten Partsch
Filed: 29 Jun 23
Utility
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18 Jan 24
A method of operating a memory controller is disclosed.
Jared L. ZERBE, Frederick A. WARE
Filed: 17 Jul 23
Utility
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18 Jan 24
A request, from a tester device, to generate a secure data asset to be securely provisioned to a target device is received by an appliance cluster.
Matthew Evan Orzen
Filed: 12 Jul 23
Utility
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11 Jan 24
A buffer integrated circuit (IC) chip is disclosed.
Evan Lawrence Erickson, Christopher Haywood, Craig E. Hampel
Filed: 6 Jul 23
Utility
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11 Jan 24
A multi-host processing system may access memory devices (e.g., memory modules, memory integrated circuits, etc.) via memory nodes having memory controllers.
Craig E. HAMPEL, John Eric LINSTADT
Filed: 16 Nov 21
Utility
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11 Jan 24
When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated.
Evan Lawrence ERICKSON, John Eric LINSTADT
Filed: 24 Jun 23
Utility
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11 Jan 24
An apparatus and method for flexible metadata allocation and caching.
Taeksang Song, Steven Woo, Craig Hampel, John Eric Linstadt
Filed: 7 Jul 23
Utility
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4 Jan 24
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware, Kenneth L. Wright
Filed: 3 Apr 23
Utility
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4 Jan 24
In a general aspect, a network interface capable of processing network traffic conforming to a Time Sensitive Network (TSN) standard and a Media Access Control layer security (MACsec) standard, comprises, within an ingress path, a Physical Coding Sublayer (PCS) connected to receive a traffic stream from a network link; a Media Access Control (MAC) unit configured to split the traffic stream into a preemptable packet stream and an express packet stream; and a MACsec unit connected between the PCS and the MAC unit, configured to operate on individual fragments of a preempted MACsec protected packet in the traffic stream to produce a traffic stream with unprotected fragments for the MAC unit.
Maksym DEMCHENKO
Filed: 9 Dec 21
Utility
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28 Dec 23
Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals.
Shahram NIKOUKARY, Jonghyun CHO, Nitin JUNEJA, Ming LI
Filed: 5 Jul 23
Utility
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28 Dec 23
A device includes a cache memory and a memory controller coupled to the cache memory.
Michael Miller, Dennis Doidge, Collins Williams
Filed: 26 Jun 23
Utility
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28 Dec 23
A method of operation of a flash integrated circuit (IC) memory device is described.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 29 Jun 23
Utility
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28 Dec 23
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports.
Richard E. Perego, Frederick A. Ware
Filed: 23 Jun 23
Utility
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21 Dec 23
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal.
Jun Kim, Pak Shing Chau, Wayne S. Richardson
Filed: 7 Jun 23
Utility
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21 Dec 23
Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability.
Aws Shallal, Micheal Miller, Stephen Horn
Filed: 22 Jun 23
Utility
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21 Dec 23
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller.
Frederick A. Ware, Holden Jessup
Filed: 24 Apr 23
Utility
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21 Dec 23
A system that calibrates timing relationships between signals involved in performing write operations is described.
Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
Filed: 14 Jun 23
Utility
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21 Dec 23
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices.
Ian Shaeffer, Ely Tsem, Craig Hampel
Filed: 23 Jun 23