696 patents
Page 2 of 35
Utility
Flash Memory Device with Photon Assisted Programming
21 Dec 23
A flash memory cell of a flash memory device is illuminated with light during programming and/or erasing.
Mark D. KELLAM
Filed: 5 Oct 21
Utility
Configurable, Power Supply Voltage Referenced Single-ended Signaling with Esd Protection
21 Dec 23
A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage.
John W. POULTON, Frederick A. WARE, Carl W. WERNER
Filed: 10 May 23
Utility
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14 Dec 23
Technologies for detecting an error using a message authentication code (MAC) associated with cache line data and differentiating the error as having been caused by an attack on memory or a MAC verification failure caused by an ECC escape.
Evan Lawrence Erickson, Helena Handschuh, Michael Alexander Hamburg, Mark Evan Marson, Michael Raymond Miller
Filed: 26 May 23
Utility
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7 Dec 23
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die.
Yohan Frans
Filed: 10 May 23
Utility
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7 Dec 23
A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate.
Thomas VOGELSANG, Torsten PARTSCH
Filed: 6 Jun 23
Utility
hsa24u0b3fye53l5cpa8lj1zolsxaxm2ipp kk7ji4nabtihglz
7 Dec 23
Aspects and implementations include systems and techniques for encryption and decryption of error-corrected codewords for combined protection against corruption of data and adversarial attacks, including obtaining a block of data that has a first plurality of symbols, generating, based on the first plurality of symbols, a second plurality of symbols, wherein the second plurality of symbols includes one or more error correction symbols for the first plurality of symbols, encrypting the second plurality of symbols using a set of symbol-level ciphers (SLCs) to obtain an encrypted plurality of symbols, and using the encrypted plurality of symbols in a computer operation.
Michael Alexander Hamburg
Filed: 1 Jun 23
Utility
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7 Dec 23
A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag.
Frederick A. Ware
Filed: 14 Jun 23
Utility
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30 Nov 23
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift.
Craig E. Hampel, Frederick A. Ware, Richard E. Perego
Filed: 23 Apr 23
Utility
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30 Nov 23
A receiver utilizes loop-unrolled decision feedback equalization (DFE).
Mohammad Sadegh JALALI, Marcus VAN IERSSEL
Filed: 27 Apr 23
Utility
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23 Nov 23
A value corresponding to an input for a cryptographic operation may be received.
Michael Tunstall, Francois Durvaux
Filed: 5 Apr 23
Utility
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23 Nov 23
An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory.
Evan Lawrence Erickson, Christopher Haywood
Filed: 11 Oct 21
Utility
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23 Nov 23
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems.
Frederick A. Ware, John Eric Linstadt, Kenneth L. Wright
Filed: 30 May 23
Utility
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23 Nov 23
A method of operation in an integrated circuit (IC) memory device is disclosed.
Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
Filed: 24 Apr 23
Utility
mjpty11r5838qacdo60fyju3aa0v2g4dm7gudyli2sj7f
23 Nov 23
A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other.
Robert WANG, Zhuobin LI, Navid YAGHINI, Hemesh YASOTHARAN, Clifford TING
Filed: 19 May 23
Utility
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23 Nov 23
A micro-threaded memory device.
Frederick A. Ware, Craig E. Hampel, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai
Filed: 23 Jun 23
Utility
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9 Nov 23
A memory is disclosed that includes a logic die having first and second memory interface circuits.
Scott C. Best, Ming Li
Filed: 10 May 23
Utility
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9 Nov 23
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices.
Frederick A. Ware, James E. Harris
Filed: 30 May 23
Utility
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9 Nov 23
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces.
Kenneth L. Wright, Frederick A. Ware
Filed: 30 May 23
Utility
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9 Nov 23
A buffer/interface device of a memory node reads a block of data (e.g., page).
Evan Lawrence ERICKSON, Christopher HAYWOOD
Filed: 27 Apr 23
Utility
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9 Nov 23
A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM).
Frederick A. Ware, John Eric Linstadt, Christopher Haywood
Filed: 30 May 23