1391 patents
Utility
High-Performance, High-Capacity Memory Systems and Modules
18 Jan 24
Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity.
Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Craig E. Hampel, Scott C. Best, John Yan
Filed: 4 Aug 23
Utility
Folded Memory Modules
18 Jan 24
A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories.
Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
Filed: 20 Jul 23
Utility
Low Power Memory with On-demand Bandwidth Boost
18 Jan 24
In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval.
Torsten Partsch
Filed: 29 Jun 23
Utility
Low-power Source-synchronous Signaling
18 Jan 24
A method of operating a memory controller is disclosed.
Jared L. ZERBE, Frederick A. WARE
Filed: 17 Jul 23
Utility
Securely Provisioning a Secure Data Asset to a Target Device Using an Authorization Token
18 Jan 24
A request, from a tester device, to generate a secure data asset to be securely provisioned to a target device is received by an appliance cluster.
Matthew Evan Orzen
Filed: 12 Jul 23
Utility
Forwarding signal supply voltage in data transmission system
16 Jan 24
In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit.
Scott C. Best, John W. Poulton
Filed: 10 Feb 22
Utility
Direct digital sequence detection and equalization
16 Jan 24
Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel.
Masum Hossain, Maruf H. Mohammad
Filed: 12 Aug 21
Utility
Dynamically Configurable Memory Error Control Schemes
11 Jan 24
A multi-host processing system may access memory devices (e.g., memory modules, memory integrated circuits, etc.) via memory nodes having memory controllers.
Craig E. HAMPEL, John Eric LINSTADT
Filed: 16 Nov 21
Utility
Selectable Multi-stage Error Detection and Correction
11 Jan 24
When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated.
Evan Lawrence ERICKSON, John Eric LINSTADT
Filed: 24 Jun 23
Utility
Compressed Memory Buffer Device
11 Jan 24
A buffer integrated circuit (IC) chip is disclosed.
Evan Lawrence Erickson, Christopher Haywood, Craig E. Hampel
Filed: 6 Jul 23
Utility
Flexible Metadata Allocation and Caching
11 Jan 24
An apparatus and method for flexible metadata allocation and caching.
Taeksang Song, Steven Woo, Craig Hampel, John Eric Linstadt
Filed: 7 Jul 23
Utility
Partial array refresh timing
9 Jan 24
A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed.
Liji Gopalakrishnan, Thomas Vogelsang, John Eric Linstadt
Filed: 3 Dec 20
Utility
Detection of a netlist version in a security chip
9 Jan 24
A pattern detector circuit is provided in a security chip, wherein the pattern detector circuit monitors accesses of a plurality of configuration registers, each of the plurality of configuration registers having a corresponding address.
Scott C. Best, Christopher Leigh Rodgers
Filed: 4 Sep 20
Utility
Interface for Memory Readout from a Memory Component In the Event of Fault
4 Jan 24
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware, Kenneth L. Wright
Filed: 3 Apr 23
Utility
NETWORK INTERFACE SUPPORTING TIME SENSITIVE NETWORKS AND MACsec PROTECTION
4 Jan 24
In a general aspect, a network interface capable of processing network traffic conforming to a Time Sensitive Network (TSN) standard and a Media Access Control layer security (MACsec) standard, comprises, within an ingress path, a Physical Coding Sublayer (PCS) connected to receive a traffic stream from a network link; a Media Access Control (MAC) unit configured to split the traffic stream into a preemptable packet stream and an express packet stream; and a MACsec unit connected between the PCS and the MAC unit, configured to operate on individual fragments of a preempted MACsec protected packet in the traffic stream to produce a traffic stream with unprotected fragments for the MAC unit.
Maksym DEMCHENKO
Filed: 9 Dec 21
Utility
Buffer access for side-channel attack resistance
2 Jan 24
A cryptographic accelerator (processor) retrieves data blocks for processing from a memory.
Andrew John Leiserson, Mark Evan Marson
Filed: 7 Jul 20
Utility
High level instructions with lower-level assembly code style primitives within a memory appliance for accessing memory
2 Jan 24
A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller.
Keith Lowery, Vlad Fruchter
Filed: 23 Sep 21
Utility
Masked gate logic for resistance to power analysis
2 Jan 24
A method of and system for gate-level masking of secret data during a cryptographic process is described.
Andrew John Leiserson, Mark Evan Marson, Megan Anneke Wachs
Filed: 11 Jul 22
Utility
Using cryptographic blinding for efficient use of montgomery multiplication
2 Jan 24
Aspects of the present disclosure involves receiving an input message, generating a first random value that is used to blind the input message to prevent a side-channel analysis (SCA) attack, computing a second random value using the first random value and a factor used to compute the Montgomery form of a blinded input message without performing an explicit Montgomery conversion of the input message, and computing a signature using Montgomery multiplication, of the first random value and the second random value, wherein the signature is resistant to the SCA attack.
Michael Tunstall
Filed: 5 Dec 22
Utility
Efficient side-channel-attack-resistant memory encryptor based on key update
2 Jan 24
Disclosed are memory encryption systems and methods that rotate encryption keys for robust resistance against side-channel-analysis (SCA)-based attacks on communication paths between an encryption engine within a trust boundary and an external memory component.
Mark Evan Marson, Michael Hutter, Bart Stevens
Filed: 4 Apr 20