1391 patents
Page 4 of 70
Utility
High capacity memory system using standard controller component
21 Nov 23
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode).
Frederick A. Ware, Suresh Rajan, Scott C. Best
Filed: 30 Jan 23
Utility
Dram device with multiple voltage domains
21 Nov 23
A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device.
Thomas Vogelsang
Filed: 26 Nov 19
Utility
System including hierarchical memory modules having different types of integrated circuit memory devices
21 Nov 23
Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path.
Craig Hampel, Mark Horowitz
Filed: 21 Aug 20
Utility
Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules
14 Nov 23
The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs).
Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright
Filed: 19 May 22
Utility
Protocol including a command-specified timing reference signal
14 Nov 23
Apparatus and methods for operation of a memory controller, memory device and system are described.
Ian Shaeffer, Thomas J. Giovannini
Filed: 3 Mar 21
Utility
Multi-die Memory Device
9 Nov 23
A memory is disclosed that includes a logic die having first and second memory interface circuits.
Scott C. Best, Ming Li
Filed: 10 May 23
Utility
Memory Systems and Methods for Improved Power Management
9 Nov 23
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices.
Frederick A. Ware, James E. Harris
Filed: 30 May 23
Utility
Fault Tolerant Memory Systems and Components with Interconnected and Redundant Data Interfaces
9 Nov 23
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces.
Kenneth L. Wright, Frederick A. Ware
Filed: 30 May 23
Utility
Compression Via Deallocation
9 Nov 23
A buffer/interface device of a memory node reads a block of data (e.g., page).
Evan Lawrence ERICKSON, Christopher HAYWOOD
Filed: 27 Apr 23
Utility
Nonvolatile Physical Memory with DRAM Cache
9 Nov 23
A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM).
Frederick A. Ware, John Eric Linstadt, Christopher Haywood
Filed: 30 May 23
Utility
Clock Generation for Timing Communications with Ranks of Memory Devices
9 Nov 23
A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal.
Jared L. Zerbe, Ian P. Shaeffer, John Eble
Filed: 14 Apr 23
Utility
Signaling Compression and Decompression Associated with a Partially Unrolled Decision Feedback Equalizer (Dfe)
9 Nov 23
Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described.
Ehud Nir
Filed: 3 May 23
Utility
Noise reducing receiver
7 Nov 23
Disclosed is receiver for a noise limited system.
Masum Hossain, Carl W. Werner
Filed: 22 Dec 21
Utility
Overdriven switch
7 Nov 23
An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts.
Frederick A. Ware, Carl W. Werner
Filed: 20 Sep 21
Utility
Outputting a key based on an authorized sequence of operations
7 Nov 23
Values and a sequence of operations associated with generating a key may be received.
Megan Anneke Wachs, Ambuj Kumar, Benjamin Che-Ming Jun
Filed: 10 Feb 20
Utility
Data-buffer component with variable-width data ranks and configurable data-rank timing
7 Nov 23
A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules.
Thomas J. Giovannini, John Eric Linstadt, Catherine Chen
Filed: 22 Feb 22
Utility
Memory system with threaded transaction support
7 Nov 23
Memory modules, systems, memory controllers and associated methods are disclosed.
Frederick A. Ware, Ely Tsern
Filed: 27 Jan 22
Utility
PAM-4 Dfe Architectures with Symbol-transition Dependent Dfe Tap Values
2 Nov 23
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel.
Masum HOSSAIN, Nhat NGUYEN, Yikui Jen DONG, Arash ZARGARAN-YAZD, Wendemagegnehu BEYENE
Filed: 8 May 23
Utility
Providing Access to a Hardware Resource Based on a Canary Value
2 Nov 23
A container corresponding to executable code may be received.
Michael A. Hamburg, Megan Anneke Wachs
Filed: 26 May 23
Utility
Securing Dynamic Random Access Memory (Dram) Contents to Non-volatile In a Persistent Memory Module
2 Nov 23
Technologies for securing dynamic random access memory contents to nonvolatile memory in a persistent memory module are described.
Taeksang Song, Evan Lawrence Erickson, Craig E. Hampel
Filed: 25 Apr 23