1391 patents
Page 6 of 70
Utility
Dram with Command-differentiated Storage of Internally and Externally Sourced Data
12 Oct 23
A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface.
Thomas J. Sheffler, Lawrence Lai, Liang Peng, Bohuslav Rychlik
Filed: 15 Jun 23
Utility
Integrity and Data Encryption (Ide) Buffer Device with Low-latency Containment Mode
12 Oct 23
A buffer integrated circuit (IC) chip is disclosed.
Evan Lawrence Erickson, John Eric Linstadt
Filed: 3 Apr 23
Utility
Memory Component with Staggered Power-down Exit
12 Oct 23
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event.
Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
Filed: 30 Jan 23
Utility
Error-correction-detection coding for hybrid memory module
10 Oct 23
A hybrid volatile/non-volatile memory employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM).
Frederick A. Ware
Filed: 27 Jan 22
Utility
Memory module with dedicated repair devices
10 Oct 23
A memory module includes a substrate, and respective first, second and third memory devices.
Frederick A. Ware, Brent S. Haukness, John Eric Linstadt, Scott C. Best
Filed: 13 May 22
Utility
Memory module with configurable command buffer
10 Oct 23
A memory module includes memory devices and a configurable command buffer that selects between alternative command ports for controlling different groupings of the memory devices.
Liji Gopalakrishnan, Ian Shaeffer, Yi Lu
Filed: 26 May 22
Utility
Memory device comprising programmable command-and-address and/or data interfaces
10 Oct 23
A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described.
Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
Filed: 19 Nov 21
Utility
Controller to detect malfunctioning address of memory device
10 Oct 23
A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command.
Adrian E. Ong, Fan Ho
Filed: 13 Apr 22
Utility
Circuits and methods for sample timing in correlated and uncorrelated signaling environments
10 Oct 23
A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module.
Panduka Wijetunga, Marcial Chua, Srinivas Satish Babu Bamdhamravuri, Abhishek Desai, Philip Lu, Cosmin Iorga
Filed: 18 Nov 21
Utility
Energy-Efficient Error-Correction-Detection Storage
5 Oct 23
A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data.
Frederick A. Ware, John E. Linstadt, Liji Gopalakrishnan
Filed: 25 Apr 23
Utility
Off-module Data Buffer
5 Oct 23
In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board.
Frederick A. Ware, Christopher Haywood
Filed: 1 Mar 23
Utility
Refresh Management Selection
5 Oct 23
Refresh management commands are issued to a memory device in order to cause the refresh of rows in the vicinity of one or more rows being “hammered.” These refresh management commands are each associated with respective row addresses that indicates the row(s) to be refreshed in order to mitigate the likelihood of data being corrupted by “row hammer.” In an embodiment, the refresh management commands are issued in response to a varying number of activate (ACT) commands having been issued since the last refresh management command.
Steven C. WOO, Taeksang SONG
Filed: 14 Mar 23
Utility
Command/address Channel Error Detection
5 Oct 23
A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times.
John Eric LINSTADT, Frederick A. WARE
Filed: 14 Mar 23
Utility
Stacked memory device with paired channels
3 Oct 23
A stacked memory device includes memory dies over a base die.
Thomas Vogelsang
Filed: 18 May 21
Utility
Memory controller with error detection and retry modes of operation
3 Oct 23
A memory system includes a link having at least one signal line and a controller.
Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
Filed: 28 Feb 20
Utility
Memory module for platform with non-volatile storage
3 Oct 23
A system that includes a non-volatile memory subsystem having non-volatile memory.
Aws Shallal, Nigel Alvares, Sarvagya Kochak
Filed: 11 Jan 22
Utility
Receiver with improved noise immunity
3 Oct 23
A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection.
Panduka Wijetunga
Filed: 12 May 22
Utility
Internet of things (IoT) device management
3 Oct 23
The embodiments described herein describe technologies to address initial establishment of device credentials in an Internet of Things (IoT) infrastructure.
Denis Alexandrovich Pochuev, Michael A. Hamburg, Pankaj Rohatgi, Amit Kapoor, Joel Patrick Wittenauer
Filed: 14 Jun 18
Utility
Inter-server Memory Pooling
28 Sep 23
A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer.
Christopher Haywood, Evan Lawrence Erickson
Filed: 9 Jan 23
Utility
Memory Module Register Access
28 Sep 23
During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number.
Thomas J. GIOVANNINI, Catherine CHEN, Scott C. BEST, John Eric LINSTADT, Frederick A. WARE
Filed: 3 Jan 23