1391 patents
Page 8 of 70
Utility
Folded memory modules
12 Sep 23
A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories.
Amir Amirkhany, Suresh Rajan, Ravindranath Kollipara, Ian Shaeffer, David A. Secker
Filed: 29 Jun 22
Utility
Deterministic operation of storage class memory
12 Sep 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware, Brent Haukness
Filed: 7 Apr 22
Utility
Performing cryptographic data processing operations in a manner resistant to external monitoring attacks
12 Sep 23
Systems and methods for performing cryptographic data processing operations in a manner resistant to external monitoring attacks.
Sami James Saab, Pankaj Rohatgi, Craig E. Hampel
Filed: 15 Dec 20
Utility
Dedicated Cache-related Block Transfer In a Memory System
7 Sep 23
A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit.
Liji Gopalakrishnan
Filed: 3 Mar 23
Utility
Protocol for Memory Power-mode Control
7 Sep 23
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data.
Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
Filed: 9 Mar 23
Utility
Data write from pre-programmed register
5 Sep 23
A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links.
Thomas J. Sheffler, Lawrence Lai, Liang Peng, Bohuslav Rychlik
Filed: 2 Dec 21
Utility
Secure asset management system
5 Sep 23
A system can include a processor having a secure mode and a non-secure mode, and a secure module configured to respond to tokens posted by the processor in the secure mode.
Gijs Willemse, Marc Van Hoorn, Marcel Van Loon
Filed: 5 Apr 21
Utility
Low-power source-synchronous signaling
5 Sep 23
A method of operating a memory controller is disclosed.
Jared L. Zerbe, Frederick A. Ware
Filed: 8 Nov 21
Utility
Signal receiver with skew-tolerant strobe gating
5 Sep 23
A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.
Neeraj Purohit, Navin Mishra, Anirudha Shelke
Filed: 21 Jun 22
Utility
Edge enhancement for signal transmitter
5 Sep 23
A signal transmitter circuit includes an output driver circuit configured to transmit a signal using a multi-level pulse amplitude modulation (PAM) scheme comprising a plurality of discreet signal levels.
Kamran Farzan, Dongyun Lee
Filed: 13 Jul 22
Utility
Low power edge and data sampling
5 Sep 23
An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal.
Jared L. Zerbe
Filed: 21 Feb 22
Utility
Efficient Storage of Error Correcting Code Information
31 Aug 23
Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel.
Amit KEDIA, Kartik Dayalal KARIYA, Sreeja MENON, Steven C. WOO
Filed: 16 Feb 23
Utility
Strobe-offset Control Circuit
31 Aug 23
A method of operation in a memory controller is disclosed.
Scott C. Best
Filed: 9 Jan 23
Utility
Low power memory with on-demand bandwidth boost
22 Aug 23
In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval.
Torsten Partsch
Filed: 25 Feb 20
Utility
Buffer circuit with adaptive repair capability
22 Aug 23
A buffer circuit is disclosed.
Scott C. Best, John Eric Linstadt, Paul William Roukema
Filed: 2 Dec 22
Utility
Flash memory device having a calibration mode
22 Aug 23
A method of operation of a flash integrated circuit (IC) memory device is described.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 15 Dec 22
Utility
Near-memory compute module
22 Aug 23
Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices).
David Wang, Nirmal Saxena
Filed: 16 Jan 19
Utility
Memory repair method and apparatus based on error code tracking
22 Aug 23
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer.
Frederick A. Ware, Ely Tsern
Filed: 28 Jun 22
Utility
Data Destruction
17 Aug 23
A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block.
Torsten PARTSCH, John Eric LINSTADT, Helena HANDSCHUH
Filed: 31 Jan 23
Utility
Memory Module with Programmable Command Buffer
17 Aug 23
A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages.
Aws Shallal, Larry Grant Giddens
Filed: 21 Feb 23