1391 patents
Page 12 of 70
Utility
Memory subsystem for a cryogenic digital system
16 May 23
The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain.
Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
Filed: 27 Aug 21
Utility
Power Efficient Circuits and Methods for Phase Alignment
11 May 23
A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements.
Pavan Kumar Kasibhatla, Jitendra Mishra
Filed: 27 Oct 22
Utility
Methods and Apparatuses for Addressing Memory Caches
11 May 23
A cache memory includes cache lines to store information.
Trung Diep, Hongzhong Zheng
Filed: 14 Nov 22
Utility
Energy efficient storage of error-correction-detection information
9 May 23
Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently.
Michael Raymond Miller, Stephen Magee, John Eric Linstadt
Filed: 2 May 22
Utility
Dynamic processing speed
9 May 23
Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack.
Steven C. Woo, Thomas Vogelsang, Joseph James Tringali, Pooneh Safayenikoo
Filed: 19 Oct 21
Utility
Protocol including timing calibration between memory request and data transfer
9 May 23
The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller.
Frederick A. Ware, Holden Jessup
Filed: 26 Jun 20
Utility
DRAM retention test method for dynamic error correction
9 May 23
A method of operation in an integrated circuit (IC) memory device is disclosed.
Ely Tsern, Frederick A Ware, Suresh Rajan, Thomas Vogelsang
Filed: 30 Apr 21
Utility
Memory system with error detection
9 May 23
A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation.
Frederick A. Ware, John Eric Linstadt
Filed: 15 Jun 22
Utility
Method and apparatus to improve connection pitch in die-to-wafer bonding
9 May 23
Semiconductor devices, packaging architectures and associated methods are disclosed.
Dongyun Lee, Ming Li
Filed: 4 Oct 21
Utility
Adjustment of multi-phase clock system
9 May 23
Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured.
Charles Walter Boecker, Roxanne Vu, Eric Douglas Groen
Filed: 10 Feb 22
Utility
Systems and Methods for Bidirectional Polarization Signaling
4 May 23
A photonic communication system in which a host communicates bidirectionally with a target via a single optical fiber using light of the same wavelength and from the same light source.
Mark D. Kellam, Carl W. Werner
Filed: 17 Oct 22
Utility
Partial Response Receiver
4 May 23
A signaling system is described.
Vladimir M. Stojanovic, Andrew C. Ho, Anthony Bessios, Bruno W. Garlepp, Grace Tsang, Mark A. Horowitz, Jared L. Zerbe, Jason C. Wei
Filed: 1 Nov 22
Utility
Managing Memory Maintenance Operations In a Memory System Having Backing Storage Media
4 May 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Collins Williams, Michael Miller, Kenneth Wright
Filed: 2 Dec 22
Utility
Packaging Techniques for Backside Mesh Connectivity
4 May 23
The embodiments herein are directed to technologies for backside security meshes of semiconductor packages.
Scott C. Best, Ming Li
Filed: 9 Nov 22
Utility
High Performance, High Capacity Memory Modules and Systems
4 May 23
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes.
Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
Filed: 18 Nov 22
Utility
Multi-processor Device with External Interface Failover
4 May 23
A multi-processor device is disclosed.
Michael Raymond Miller, Evan Lawrence Erickson
Filed: 24 Oct 22
Utility
System and method for providing a configurable timing control for a memory system
2 May 23
A system and method are directed to providing a configurable timing control of a memory system.
Michael L. Takefman, Maher Amer, Claus Reitlingshoefer, Riccardo Badalone
Filed: 9 Jul 21
Utility
Bus Distribution Using Multiwavelength Multiplexing
27 Apr 23
Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information.
Mark D. KELLAM, Dongyun LEE, Thomas VOGELSANG, Steven C. WOO
Filed: 10 Oct 22
Utility
Command/address channel error detection
25 Apr 23
A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times.
John Eric Linstadt, Frederick A. Ware
Filed: 17 May 22
Utility
Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering
25 Apr 23
A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin.
Lap Wai Chow, Bryan J. Wang, James P. Baukus, Ronald P. Cocchi
Filed: 25 Jan 21