1391 patents
Page 11 of 70
Utility
Periodic calibration for communication channels by drift tracking
30 May 23
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift.
Craig E. Hampel, Frederick A. Ware, Richard E. Perego
Filed: 13 Jan 22
Utility
Providing access to a hardware resource based on a canary value
30 May 23
A container corresponding to executable code may be received.
Michael A. Hamburg, Megan Anneke Wachs
Filed: 3 May 21
Utility
Methods and circuits for adaptive equalization
30 May 23
An integrated circuit equalizes a data signal expressed as a series of symbols.
Ramin Farjad-Rad
Filed: 23 Sep 21
Utility
Matched Digital-to-analog Converters
25 May 23
A voltage ladder is used to generate reference voltages.
Ravi SHIVNARAINE, Marcus VAN IERSSEL
Filed: 29 Nov 22
Utility
Entropy Distribution
25 May 23
Technologies for selectively distributing a same random number to multiple cryptographic circuits are described.
Winthrop Wu, Scott C. Best
Filed: 17 Nov 22
Utility
Secure Key Exchange In a Multi-processor Device
25 May 23
An integrated circuit comprises an interface controller to receive a message, wherein at least a portion of the message is encrypted, a primary processor coupled to the interface controller and configured to process the received message, and a secondary secure processor coupled to the primary processor and to the interface controller.
Evan Lawrence Erickson, Joel Wittenauer, Winthrop John Wu
Filed: 18 Nov 22
Utility
Multiple Host Memory Controller
25 May 23
Multiple (e.g., two) hosts access a single memory channel (and/or device) via a memory controller.
Thomas J. THATCHER, Bryan Jason WANG
Filed: 15 Nov 22
Utility
Redundant Data Log Retrieval In Multi-processor Device
25 May 23
A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor.
Evan Lawrence Erickson
Filed: 18 Oct 22
Utility
Error Coalescing
25 May 23
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol.
John Eric LINSTADT
Filed: 29 Nov 22
Utility
Efficient Integrity Monitoring of Processing Operations with Multiple Memory Arrays
25 May 23
Disclosed systems and techniques are directed to efficient integrity monitoring of computational operations using multiple memory arrays collectively representative of known events associated with the computational operations.
Michael Alexander Hamburg, Winthrop John Wu
Filed: 22 Nov 22
Utility
Low latency memory access
23 May 23
A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces.
Frederick A. Ware
Filed: 30 Aug 21
Utility
Remote memory selection
23 May 23
A multi-path fabric interconnected system with many nodes and many communication paths from a given source node to a given destination node.
Christopher Haywood, Evan Lawrence Erickson
Filed: 28 May 21
Utility
Multi-die memory device
23 May 23
A memory is disclosed that includes a logic die having first and second memory interface circuits.
Scott C. Best, Ming Li
Filed: 2 Dec 21
Utility
Exponent splitting for cryptographic operations
23 May 23
A first share value and a second share value may be received.
Michael Tunstall
Filed: 4 Jun 21
Utility
Cache Memory That Supports Tagless Addressing
18 May 23
The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing.
Hongzhong Zheng, Trung A. Diep
Filed: 22 Nov 22
Utility
Stacked-Die Neural Network with Integrated High-Bandwidth Memory
18 May 23
A neural-network accelerator die is stacked on and integrated with a high-bandwidth memory so that the stack behaves as a single, three-dimensional (3-D) integrated circuit.
Thomas Vogelsang, Steven Woo, Liji Gopalakrishnan
Filed: 23 Mar 21
Utility
Authentication Using an Ephemeral Asymmetric Keypair
18 May 23
A prover chip uses a key multiplier value generated by a proof-of-work function from a challenge value, a random number, and elliptic curve cryptography (ECC) techniques to generate a one-time (or ephemeral) use private key.
Mark Evan MARSON, Scott C. BEST
Filed: 26 Mar 21
Utility
Local internal discovery and configuration of individually selected and jointly selected devices
16 May 23
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller.
John Eric Linstadt
Filed: 23 Nov 21
Utility
Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die
16 May 23
A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die.
Yohan Frans
Filed: 28 Dec 20
Utility
Fractional program commands for memory devices
16 May 23
A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command.
Brent S. Haukness, Ian Shaeffer, Gary Bela Bronner
Filed: 19 Nov 20