1391 patents
Page 13 of 70
Utility
Multi-Stage Equalizer for Inter-Symbol Interference Cancellation
20 Apr 23
An equalizer includes a first feed-forward stage that provides a measure of low-frequency ISI and a second feed-forward stage that includes a cascade of stages each making an ISI estimate .
Prashant Choudhary, Nanyang Wang
Filed: 1 Nov 22
Utility
Flash Memory Device Having a Calibration Mode
20 Apr 23
A method of operation of a flash integrated circuit (IC) memory device is described.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 15 Dec 22
Utility
6jwkk54oz4xqeyai726o1i9oxl50x3ldkm691uj5md4eov0u0bbvfoak
20 Apr 23
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die.
Frederick A. Ware, Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil
Filed: 13 Oct 22
Utility
f9uf4do7uj067rfw35t2ug8gkdtxdu5sgp030onjh60lu8tek5377
18 Apr 23
Memory devices and a memory controller that controls such memory devices.
Frederick Ware
Filed: 8 Nov 21
Utility
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18 Apr 23
A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal.
Jared L. Zerbe, Ian P. Shaeffer, John Eble
Filed: 6 Jul 20
Utility
iu893l0rv8fbqsqzjrdibwihfh5mvr2pfq w9re0rt396quhjbahddp2a
13 Apr 23
Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described.
Lei Luo, John Eble
Filed: 7 Oct 22
Utility
90wy5yy2gi7vy0peowmcu0gyntsc0su
11 Apr 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware, Kenneth L. Wright
Filed: 7 Apr 22
Utility
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11 Apr 23
Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down.
Panduka Wijetunga, Dhiraj Kumar
Filed: 4 Aug 21
Utility
wwbj77u4yg7fddc0ku43o
11 Apr 23
A value corresponding to an input for a cryptographic operation may be received.
Michael Tunstall, Francois Durvaux, Jr.
Filed: 3 Dec 15
Utility
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6 Apr 23
A power converter includes a plurality of power stages configured to generate an output current that has an output voltage, based on an input current that as an input voltage.
Gaurav Bawa, Panduka Wijetunga
Filed: 4 Oct 22
Utility
7gqy56bglnd9n8b80yp1g5dvbyq21pmdw5dlfdw27z9tozjezbjlv
6 Apr 23
The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device.
Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
Filed: 19 Aug 22
Utility
nw2s4z6lnjklovnj0fyiejmvfz69cj8e m7kp7gaimt7ib0y06w5rxx4axw
6 Apr 23
An integrated circuit (IC) memory controller is disclosed.
Jade M. Kizer, Sivakumar Doraiswamy, Benedict Lau
Filed: 15 Sep 22
Utility
dqhi4uojd40n72j0sgwvp390fdcasmufqwko870qvbukgc0
4 Apr 23
A first input share value, a second input share value, and a third input share value may be received.
Michael Hutter, Michael Tunstall
Filed: 16 Dec 20
Utility
0fn74fjyl8mzwjgrme7j69pemz7kgz
4 Apr 23
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data.
Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Frederick A. Ware, Lawrence Lai, Kishore Ven Kasamsetty
Filed: 4 Jan 22
Utility
0lvehu0frlsnqqir10gf5wesfnrr63kkd7ubbe2h25izr0soy0xrn05
30 Mar 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware
Filed: 27 Sep 22
Utility
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30 Mar 23
A memory module includes a substrate, plural memory devices, and a buffer.
Frederick A. Ware, Craig E. Hampel
Filed: 30 Sep 22
Utility
6q5m0llduwqptru7fhgbohkw0vpysgaj55tu454qiq8q09exl6othri
30 Mar 23
An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies.
Dongyun LEE, Carl W. WERNER, Torsten PARTSCH
Filed: 9 Sep 22
Utility
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30 Mar 23
A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory.
Ian Shaeffer, Frederick A. Ware
Filed: 15 Sep 22
Utility
3hj79glvis0r7tu7j1g072u3xpp8gms9ljrgprg3dcc xrda9dlew48
28 Mar 23
A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages.
Aws Shallal, Larry Grant Giddens
Filed: 3 May 21
Utility
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23 Mar 23
Aspects of the present disclosure involve a method and a system to perform the method to obtain a cryptographic output of a plurality of rounds of a cipher, by performing a plurality of modified rounds of the cipher, each of the modified rounds computing an unmasking transform, an operation of a respective round of the cipher, and a masking transform, the unmasking transform being an inverse of the masking transform of a previous round of the cipher.
Michael Alexander Hamburg, Helena Handschuh, Mark Evan Marson, Winthrop John Wu
Filed: 19 Sep 22