1391 patents
Page 15 of 70
Utility
Authentication Timers
16 Feb 23
A first device transmits a first message to a second device as part of a challenge-response protocol in order to authenticate the second device.
Scott C. BEST, Matthew E. ORZEN
Filed: 11 Jan 21
Utility
Managing Privileges of Different Entities for an Integrated Circuit
16 Feb 23
A request associated with one or more privileges assigned to a first entity may be received.
Benjamin Che-Ming JUN, William Craig RAWLINGS, Ambuj KUMAR, Mark Evan MARSON
Filed: 29 Jul 22
Utility
6nopb3ayhxfj0fe1t0qlu7zyylunzpdxb7d9
16 Feb 23
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel.
Anirudha SHELKE, Ashwin S. MADHAVAKAIMAL, Kiran BABY
Filed: 2 Aug 22
Utility
viqm7b0vh6hy2k38 c49famlv2tfrhjx29dol
16 Feb 23
A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus.
Pravin Kumar Venkatesan, Liji Gopalakrishnan, Kashinath Ullhas Prabhu, Makarand Ajit Shirasgaonkar
Filed: 24 Jun 22
Utility
umjiqa8h0icbln9ivitlocgcxnc2lyd1sl5llahr
16 Feb 23
In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal.
Frederick A. Ware, John Eric Linstadt, Carl W. Werner
Filed: 22 Aug 22
Utility
uv47m3im5wrfxnohpxqntdzg y9zfxqer2zzto
14 Feb 23
Systems and methods are provided for detecting and correcting address errors in a memory system.
Ian Shaeffer, Craig E. Hampel
Filed: 21 Sep 21
Utility
6lf9s9obpy246sgq f8ep9t
14 Feb 23
A secret key value that is inaccessible to software is scrambled according to registers consisting of one-time programmable (OTP) bits.
Ambuj Kumar, Ronald Perez
Filed: 11 Dec 20
Utility
fk2bz6jf5je094yusy5b2dpwblg0tnbt201c
14 Feb 23
Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process.
Nanyan Wang, Vadim Moshinsky, Prashant Choudhary
Filed: 14 Jan 22
Utility
62ed5bd1kyk7kgaicm2xd29fnvfnnw
9 Feb 23
Aspects of the present disclosure involve techniques and cryptographic processors configured to perform the techniques that include sign-efficient addition and subtraction operations that use Montgomery reduction and are capable of facilitating fast streaming operations.
Michael Alexander Hamburg, Lauren De Meyer, Arvind Singh
Filed: 14 Jul 22
Utility
6i2ed3bzc23eg4l8zxxqi02tvmk0z0i8n6
7 Feb 23
During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number.
Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
Filed: 21 Apr 21
Utility
zqmjbk6h02npg1asctgd467 6wmfdxm
7 Feb 23
A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory.
Frederick A. Ware
Filed: 30 Jun 21
Utility
2az3z0himaomp0k5vrigr8siqv55fgy tvh
7 Feb 23
A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry.
Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
Filed: 10 May 21
Utility
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31 Jan 23
A baud-rate phase detector uses two error samplers.
Marcus Van Ierssel
Filed: 28 May 21
Utility
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31 Jan 23
A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event.
Frederick A. Ware
Filed: 23 Mar 22
Utility
u7t4n1si0gku7xymmynvocmgirdkhz97nze7r1p5skp0vrt023w9vl9zy
31 Jan 23
A memory allocation device on an originating node requests an allocation of memory from a remote node.
Evan Lawrence Erickson, Christopher Haywood
Filed: 28 May 21
Utility
4dafus9pamyh24fxkledr
31 Jan 23
A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit.
Scott C. Best
Filed: 13 Jan 22
Utility
k56r3j6gahfez61qdc86ldhiqwigbzuow1cithpxg46fps9i
31 Jan 23
A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer.
Christopher Haywood, Evan Lawrence Erickson
Filed: 29 Oct 20
Utility
ohh9yc2wo9w6mok144mderw4vcoqdtu9bmy6s2p9vr1dd62 wbee7l
31 Jan 23
Described are technologies of all-digital camouflage circuits.
Scott C. Best
Filed: 15 Aug 19
Utility
41cdg6xj1d0bv8eklw31s bxaqpfhgtet7e8chayuecq8
31 Jan 23
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode).
Frederick A. Ware, Suresh Rajan, Scott C. Best
Filed: 28 May 21
Utility
sa8bqioiuxbov5cuvzr8hmldhwsnc9kezuthhzf6xqs9axkyoddos3yb
26 Jan 23
A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer.
Frederick A. Ware, Ely Tsern
Filed: 28 Jun 22