1391 patents
Page 7 of 70
Utility
Local Internal Discovery and Configuration of Individually Selected and Jointly Selected Devices
28 Sep 23
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller.
John Eric Linstadt
Filed: 3 Apr 23
Utility
Memory System with Error Detection
28 Sep 23
A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation.
Frederick A. Ware, John Eric Linstadt
Filed: 4 Apr 23
Utility
High Performance, Non-volatile Memory Module
28 Sep 23
Memory controllers, devices, modules, systems and associated methods are disclosed.
Frederick A. Ware, Ely Tsern, John Eric Linstadt
Filed: 9 Jan 23
Utility
Maintaining secure session state with failover during endpoint provisioning
26 Sep 23
The embodiments described herein describe technologies to maintaining a secure session state with failover during endpoint provisioning.
Denis Alexandrovich Pochuev
Filed: 24 Aug 21
Utility
Training and operations with a double buffered memory topology
26 Sep 23
System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology.
Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
Filed: 31 Mar 22
Utility
Methods and circuits for decision-feedback equalization with early high-order-symbol detection
26 Sep 23
A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol.
Masum Hossain, Nhat Nguyen, Charles Walter Boecker
Filed: 28 Jun 22
Utility
Multi-Element Memory Device with Power Control for Individual Elements
21 Sep 23
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry.
Deborah Lindsey Dressler, Julia Kelly Cline, Wayne Frederick Ellis
Filed: 19 Dec 22
Utility
Low Latency Memory Access
21 Sep 23
A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces.
Frederick A. WARE
Filed: 12 Apr 23
Utility
Energy Efficient Storage of Error-correction-detection Information
21 Sep 23
Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently.
Michael Raymond MILLER, Stephen MAGEE, John Eric LINSTADT
Filed: 4 Apr 23
Utility
Data-buffer Controller/control-signal Redriver
21 Sep 23
In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets.
Torsten Partsch, Shahram Nikoukary, Catherine Chen
Filed: 24 Aug 21
Utility
Area-efficient, Width-adjustable Signaling Interface
21 Sep 23
A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.
Frederick A. Ware
Filed: 16 Jan 23
Utility
Signal receiver with skew-tolerant strobe gating
19 Sep 23
A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component.
Andrew Fuller, Robert E. Palmer, Thomas J. Giovannini, Michael D. Bucher, Thoai Thai Le
Filed: 26 Aug 21
Utility
Memory component with error-detect-correct code interface
19 Sep 23
A memory component internally generates and stores the check bits of error detect and correct code (EDC).
Frederick A. Ware, Brent S. Haukness, Lawrence Lai
Filed: 29 Sep 22
Utility
Quad-channel DRAM
19 Sep 23
A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores.
Steven C. Woo, Torsten Partsch
Filed: 18 Feb 20
Utility
Secure data provisioning
19 Sep 23
A first instruction to store an entity identification (ID) in a memory of a device may be received.
Ambuj Kumar, Daniel Beitel, Benjamin Che-Ming Jun
Filed: 4 Oct 19
Utility
Edge Based Partial Response Equalization
14 Sep 23
A method is disclosed.
Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake
Filed: 13 Oct 22
Utility
Adjustable access energy and access latency memory system and devices
12 Sep 23
Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats.
Frederick A. Ware, John Eric Linstadt
Filed: 3 Jun 22
Utility
Stacked device system
12 Sep 23
Multiple device stacks are interconnected in a ring topology.
Steven C. Woo
Filed: 11 Aug 21
Utility
Memory module threading with staggered data transfers
12 Sep 23
A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed.
Hongzhong Zheng, Frederick A Ware
Filed: 13 May 22
Utility
High-performance, high-capacity memory systems and modules
12 Sep 23
Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity.
Frederick A. Ware, Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Craig E. Hampel, Scott C. Best, John Yan
Filed: 21 Oct 21