28912 patents
Page 56 of 1446
Utility
Semiconductor Device
30 Nov 23
A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.
Chung-Te LIN, Wei-Yuan LU, Feng-Cheng YANG
Filed: 31 Jul 23
Utility
Semiconductor Devices and Methods of Manufacture
30 Nov 23
A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process.
Chun-Yen Peng, Te-Yang Lai, Sai-Hooi Yeong, Chi On Chui
Filed: 9 Aug 23
Utility
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30 Nov 23
An integrated circuit (IC) with active and dummy device cell arrays and a method of fabricating the same are discloses.
Kai-Chi WU, Ching-Hung Kao, Meng-I Kang, Kuo-Fang Ting
Filed: 9 Aug 23
Utility
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30 Nov 23
Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided.
Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Yi Che Chan, Chih Ping Liao, YungHao Wang, Sen-Hong Syue
Filed: 4 Aug 23
Utility
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30 Nov 23
A method for forming a semiconductor device structure is provided.
Yi-Ruei JHAN, Kuo-Cheng CHIANG, Chih-Hao WANG
Filed: 27 May 22
Utility
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30 Nov 23
A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer.
Chih-Kai YANG, Yu-Tien SHEN, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
Filed: 10 Aug 23
Utility
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30 Nov 23
A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure.
Yu-Lien HUANG, Che-Ming HSU, Ching-Feng FU, Huan-Just LIN
Filed: 31 Jul 23
Utility
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30 Nov 23
In a method of manufacturing a semiconductor device, a target layer to be patterned is formed over a substrate, a mask layer having an opening is formed over the target layer, the opening is enlarged in a first direction without enlarging the opening in a second direction crossing the first direction by a directional process, where the first and second directions are parallel to an upper surface of the substrate, and the target layer is patterned to form a hole corresponding to the opening.
Po-Han LIN, Huan-Chieh CHANG
Filed: 31 May 22
Utility
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30 Nov 23
An IC structure includes first and second gates, first and second source regions, a shared drain region, and an isolation region.
Tian-Yu XIE, Xin-Yong WANG, Lei PAN, Kuo-Ji CHEN
Filed: 31 Jul 23
Utility
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30 Nov 23
A system for manufacturing a semiconductor device comprises an edge coating device.
Chun-Wei LIAO, Tung-Hung FENG, Hui-Chun LEE
Filed: 10 Aug 23
Utility
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30 Nov 23
A device includes a plurality of photodiode regions within a semiconductor substrate, a plurality of transistors, a plurality of deep trench isolation (DTI) structures, and a plurality of isolation structures.
Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE
Filed: 31 Jul 23
Utility
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30 Nov 23
A method of fabricating a semiconductor device includes providing a first substrate and forming a resist layer over the first substrate.
Chi-Hung LIAO, Po-Ming SHIH
Filed: 7 Aug 23
Utility
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30 Nov 23
The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform.
Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
Filed: 10 Aug 23
Utility
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30 Nov 23
Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer.
Hongfa Luan, Yi-Fan Chen, Chun-Yen Peng, Cheng-Po Chau, Wen-Yu Ku, Huicheng Chang
Filed: 25 Jul 23
Utility
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30 Nov 23
This disclosure provides for robust isolation across the SOI structure.
Lin-Chen Lu, Gulbagh Singh, Tsung-Han Tsai, Po-Jen Wang
Filed: 10 Aug 23
Utility
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30 Nov 23
To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer.
Chen-Fong TSAI, Ya-Lun CHEN, Tsai-Yu HUANG, Yahru CHENG, Huicheng CHANG, Yee-Chia YEO
Filed: 8 Aug 23
Utility
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30 Nov 23
Semiconductor structures and methods for manufacturing the same are provided.
Lin-Yu HUANG, Li-Zhen YU, Huan-Chieh SU, Chih-Hao WANG
Filed: 25 May 22
Utility
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30 Nov 23
A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.
Cheng-Hsien WU
Filed: 8 Aug 23
Utility
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30 Nov 23
A semiconductor structure includes an epitaxial region having a front side and a backside.
Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
Filed: 9 Aug 23
Utility
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30 Nov 23
Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.
Yun-Jui HE, Chih-Teng LIAO
Filed: 10 Aug 23