102 patents
Page 3 of 6
Utility
Computational Memory Cell and Processing Array Device Using the Memory Cells for Xor and Xnor Computations
22 Jul 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 2 Apr 21
Utility
Computational Memory Cell and Processing Array Device Using the Memory Cells for Xor and Xnor Computations
22 Jul 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 2 Apr 21
Utility
Results Processing Circuits and Methods Associated with Computational Memory Cells
15 Jul 21
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Bob HAIG, Eli EHRMAN, Dan ILAN, Patrick CHUANG, Chao-Hung CHANG, Mu-Hsiang HUANG
Filed: 27 Oct 20
Utility
Memory Matrix Multiplication and Its Usage In Neural Networks
8 Jul 21
A method for in memory computation of a neural network, the neural network having weights arranged in a matrix, includes previously storing the matrix in an associated memory device, receiving an input arranged in a vector and storing it in the memory device, and in-memory, computing an output of the network using the input and the weights.
Avidan AKERIB, Pat LASSERRE
Filed: 7 Mar 21
Utility
One by One Selection of Items of a Set
17 Jun 21
An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.
Moshe LAZER, Eli EHRMAN
Filed: 2 Mar 21
Utility
Orthogonal Data Transposition System and Method During Data Transfers To/from a Processing Array
10 Jun 21
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory.
Bob HAIG, Patrick CHUANG, Chih TSENG, Mu-Hsiang HUANG
Filed: 28 Oct 20
Utility
Finding K Extreme Values In Constant Processing Time
27 May 21
A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset.
Eli EHRMAN, Avidan AKERIB, Moshe LAZER
Filed: 2 Feb 21
Utility
In memory matrix multiplication and its usage in neural networks
4 May 21
A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array.
Avidan Akerib, Pat Lasserre
Filed: 23 Mar 17
Utility
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
4 May 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Eli Ehrman
Filed: 19 Sep 17
Utility
One by one selection of items of a set
23 Mar 21
A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly select a next elected item from the set.
Moshe Lazer, Eli Ehrman
Filed: 30 Aug 17
Utility
Computational memory cell and processing array device using complementary exclusive or memory cells
23 Mar 21
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean Shu, Avidan Akerib
Filed: 18 Jun 19
Utility
Concurrent Multi-bit Adder
18 Mar 21
A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the carry-out value for a first group is calculated, selecting the next group carry out value from the group carry-out predictions.
Moshe LAZER
Filed: 2 Nov 20
Utility
Precise exponent and exact softmax computation
16 Mar 21
A method for an associative memory device includes dividing a multi-bit mantissa A of a number X to a plurality of smaller partial mantissas Aj, offline calculating a plurality of partial exponents F(Aj) for each possible value of each partial mantissa Aj and storing the plurality of partial exponents F(Aj) in a look up table (LUT) of the associative memory device.
Avidan Akerib
Filed: 15 Oct 17
Utility
Method for min-max computation in associative memory
9 Mar 21
A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory array and performing a horizontal bit-wise Boolean operation on rows of the associative memory array to produce an extreme SOR (ESOR) having the extreme value.
Moshe Lazer
Filed: 16 Dec 19
Utility
Ultra low VDD memory cell with ratioless write port
9 Mar 21
An ultra low VDD memory cell has a ratioless write port.
Lee-Lean Shu, Patrick Chuang, Chao-Hung Chang
Filed: 7 Feb 20
Utility
Deduplication of Data Via Associative Similarity Search
25 Feb 21
A deduplication system includes a similarity searcher, a difference calculator, and a storage manager.
Avidan AKERIB, Dan ILAN, Eli EHRMAN, Elona EREZ
Filed: 25 Jun 20
Utility
Finding K extreme values in constant processing time
23 Feb 21
A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset.
Eli Ehrman, Avidan Akerib, Moshe Lazer
Filed: 13 Jul 17
Utility
Processing array device that performs one cycle full adder operation and bit line read/write logic features
23 Feb 21
A processing array that performs one cycle full adder operations.
Lee-Lean Shu, Bob Haig, Chao-Hung Chang
Filed: 21 Feb 20
Utility
Error detecting memory device
16 Feb 21
A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns.
Avidan Akerib
Filed: 22 Sep 20
Utility
Processing Array Device That Performs One Cycle Full Adder Operation and Bit Line Read/write Logic Features
28 Jan 21
A processing array that performs one cycle full adder operations.
Lee-Lean SHU, Bob HAIG, Chao-Hung CHANG
Filed: 6 Oct 20