102 patents
Page 5 of 6
Utility
In-memory stochastic rounder
12 Oct 20
An associative processor includes a memory array and a controller.
Samuel Lifsches
Filed: 4 Jul 18
Utility
Computational Memory Cell and Processing Array Device Using Memory Cells
23 Sep 20
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 7 Jun 20
Utility
Read data processing circuits and methods associated memory cells
14 Sep 20
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 22 Aug 18
Utility
Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
7 Sep 20
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects.
Bob Haig, Eli Ehrman, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 22 Aug 18
Utility
Computational memory cell and processing array device using memory cells
27 Jul 20
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 18 Sep 17
Utility
Systems and methods involving multi-bank, dual-pipe memory circuitry
20 Jul 20
Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed.
Mu-Hsiang Huang, Robert Haig, Patrick Chuang, Lee-Lean Shu
Filed: 4 Jun 15
Utility
Self Correcting Memory Device
17 Jun 20
A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder.
Avidan AKERIB
Filed: 16 Dec 18
Utility
Massively Parallel, Associative Multiplier-accumulator
27 May 20
An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder.
Avidan AKERIB
Filed: 25 Nov 18
Utility
Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry
18 May 20
A system, method and circuits are described that pertain to locked loop circuits, distributed duty cycle correction loop circuitry.
Yu-Chi Cheng, Patrick Chuang
Filed: 26 Jun 16
Utility
Non-destructive Memory Array to Implement a Full Adder
13 May 20
A non-destructive memory array implements a full adder.
LeeLean SHU, Avidan AKERIB
Filed: 12 Jan 20
Utility
System and method for long addition and long multiplication in associative memory
27 Apr 20
A method for an associative memory device includes replacing a set of three multi-bit binary numbers P, Q and R, stored in the associative memory device, with two multi-bit binary numbers X and Y, also stored in the associative memory device, wherein a sum of the binary numbers P, Q and R is equal to a sum of the binary numbers X and Y.
Moshe Lazer
Filed: 7 Mar 18
Utility
Results Processing Circuits and Methods Associated with Computational Memory Cells
15 Apr 20
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 12 Dec 19
Utility
Method for Min-max Computation In Associative Memory
15 Apr 20
A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory array and performing a horizontal bit-wise Boolean operation on rows of the associative memory array to produce an extreme SOR (ESOR) having the extreme value.
Moshe Lazer
Filed: 15 Dec 19
Utility
Sparse Matrix Multiplication In Associative Memory Device
25 Mar 20
A method for use in an associative memory device when multiplying by a sparse matrix includes storing only non-zero elements of the sparse matrix in the associative memory device as multiplicands.
Avidan AKERIB
Filed: 24 Nov 19
Utility
Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
23 Mar 20
A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode.
Young-Nam Oh, Soon Kyu Park, Jae Hyeong Kim
Filed: 17 Oct 17
Utility
Four steps associative full adder
13 Jan 20
A method to add a first one bit variable with a second one bit variable and a carry-in bit, to generate a sum bit and a carry-out bit, the method includes initiating the sum bit to the value of the second one bit variable, initiating the carry-out bit to a value of the carry-in bit and modifying the sum bit and the carry-out bit if a comparison of a sequence of the first one bit variable, the second one bit variable and an inverse value of the carry-in bit matches one of a predefined set of a change trigger sequences.
LeeLean Shu, Avidan Akerib
Filed: 18 Sep 17
Utility
Systems and methods of pipelined output latching involving synchronous memory arrays
13 Jan 20
Systems and methods of synchronous memories and synchronous memory operation are disclosed.
Lee-Lean Shu, Yoshinori Sato
Filed: 21 Mar 18
Utility
In-memory Stochastic Rounder
8 Jan 20
An associative processor includes a memory array and a controller.
Samuel Lifsches
Filed: 4 Jul 18
Utility
Computational memory cell and processing array device using memory cells
30 Dec 19
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 18 Sep 17
Utility
Method for min-max computation in associative memory
23 Dec 19
A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory array and performing a horizontal bit-wise Boolean operation on rows of the associative memory array to produce an extreme SOR (ESOR) having the extreme value.
Moshe Lazer
Filed: 28 Aug 17