102 patents
Page 4 of 6
Utility
Write Data Processing Methods Associated with Computational Memory Cells
28 Jan 21
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 9 Oct 20
Utility
Reference Distance Similarity Search
14 Jan 21
A similarity search system includes a database of original vectors, a hierarchical database of bins and a similarity searcher.
Dan ILAN, Amir Gottlieb
Filed: 26 Apr 20
Utility
Results processing circuits and methods associated with computational memory cells
12 Jan 21
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 4 Oct 18
Utility
Massively parallel, associative multiplier accumulator
12 Jan 21
An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder.
Avidan Akerib
Filed: 26 Nov 18
Utility
Error Detecting Memory Device
6 Jan 21
A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns.
Avidan AKERIB
Filed: 21 Sep 20
Utility
Processing array device that performs one cycle full adder operation and bit line read/write logic features
28 Dec 20
A processing array that performs one cycle full adder operations.
Lee-Lean Shu, Bob Haig, Chao-Hung Chang
Filed: 17 Jun 19
Utility
Computational Memory Cell and Processing Array Device Using Complementary Exclusive or Memory Cells
23 Dec 20
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function.
Lee-Lean SHU, Avidan AKERIB
Filed: 17 Jun 19
Utility
Computational memory cell and processing array device using memory cells
7 Dec 20
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 18 Sep 17
Utility
Orthogonal data transposition system and method during data transfers to/from a processing array
7 Dec 20
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory.
Bob Haig, Patrick Chuang, Chih Tseng, Mu-Hsiang Huang
Filed: 1 Oct 18
Utility
In-memory Computing Device for 8T-SRAM Memory Cells
2 Dec 20
An in-memory computing device includes a memory array, a multiple row decoder and a sensing circuit.
Avidan AKERIB, Eli EHRMAN
Filed: 17 Aug 20
Utility
Computational memory cell and processing array device with ratioless write port
30 Nov 20
A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell.
Patrick Chuang, Chao-Hung Chang, Lee-Lean Shu
Filed: 6 Feb 20
Utility
Pipeline Architecture for Bitwise Multiplier-accumulator (Mac)
25 Nov 20
A unit for accumulating a plurality N of multiplied M bit values includes a receiving unit, a bit-wise multiplier and a bit-wise accumulator.
Avidan Akerib
Filed: 4 Apr 20
Utility
Sparse matrix multiplication in associative memory device
23 Nov 20
A method for use in an associative memory device when multiplying by a sparse matrix includes storing only non-zero elements of the sparse matrix in the associative memory device as multiplicands.
Avidan Akerib
Filed: 24 Nov 19
Utility
Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
23 Nov 20
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 22 Aug 18
Utility
Write data processing circuits and methods associated with computational memory cells
23 Nov 20
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
Filed: 22 Aug 18
Utility
In-memory Efficient Multistep Search
18 Nov 20
A system for performing cascading search includes an associative memory array, a controller, a similarity search processor and an exact match processor.
Avidan AKERIB
Filed: 5 May 20
Utility
Non-volatile in-memory computing device
9 Nov 20
Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array.
Avidan Akerib, Eli Ehrman
Filed: 31 Dec 14
Utility
Concurrent multi-bit adder
2 Nov 20
A system includes an associative memory array and a concurrent adder.
Moshe Lazer
Filed: 28 Aug 19
Utility
Computational memory cell and processing array device using memory cells
26 Oct 20
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR.
Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
Filed: 18 Sep 17
Utility
Self correcting memory device
26 Oct 20
A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder.
Avidan Akerib
Filed: 16 Dec 18