58 patents
Page 2 of 3
Utility
Processor and pipeline processing method for processing multiple threads including wait instruction processing
21 Feb 23
A pipeline processing unit includes a fetch unit that fetches the instruction for the thread having an execution right, a decoding unit that decodes the instruction fetched by the fetch unit, and a computation execution unit that executes the instruction decoded by the decoding unit.
Kazuhiro Mima, Hitomi Shishido
Filed: 10 Jun 21
Utility
Dimming Agent and Light-emitting Device Containing Dimming Agent
5 Jan 23
A dimming agent according to one or more embodiments is disclosed that may include at least one of terbium, praseodymium, manganese, titanium.
Yousuke UMETSU, Kazuyoshi HAGA
Filed: 14 Sep 22
Utility
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29 Dec 22
A first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in layers.
Bungo TANAKA
Filed: 29 Jun 21
Utility
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27 Dec 22
A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region.
Taro Kondo
Filed: 12 Jan 21
Utility
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6 Dec 22
A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.
Yuuichi Oshino
Filed: 28 Jan 21
Utility
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27 Oct 22
An abnormality detection circuit and method of detecting an abnormality in a CPU is disclosed that may include counting a count value from an initial value to a timeout value; storing a seed value readable from the CPU; generating a key value for verification by performing a specified arithmetic processing on the seed value; waiting for a key value to be written by the CPU; comparing the key value written by the CPU with the key value for verification; and when the count value is equal to the timeout value without the counter being reset, in response to the key value and the key value for verification matching, resetting the counter and storing the seed value to be determined at the time of resetting the counter in the seed value storage section.
Naohiko SHIMOYAMA
Filed: 8 Jul 22
Utility
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15 Sep 22
An integrated circuit for digitally controlling a critical mode power factor correction (PFC) circuit according to one or more embodiments may include: an output voltage detector and a switching current detector; an A/D converter and a sample and hold circuit that perform analog-to-digital conversion of an output signal of the output voltage detector and the switching current detector; an arithmetic unit that performs calculation based on the output signal of the A/D converter and generates a pulse signal to turn on/off a switching device of the PFC circuit; a correction value calculator that calculates, based on a switching frequency of the PFC circuit, a correction value for linearly correcting the output signal of the A/D converter; and an adder that adds the correction value to the output signal of the A/D converter to correct the output signal of the A/D converter and inputs the corrected output signal to the arithmetic unit.
Osamu OHTAKE, Ryuichi FURUKOSHI
Filed: 9 Mar 22
Utility
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25 Aug 22
A method may include detecting an output voltage of the output smoothing capacitor in the bridgeless interleaved power factor correction circuit of a critical mode, comparing the detected output voltage with a reference voltage, controlling the first and the second half-bridge circuits included in the bridgeless interleaved power factor correction circuit of the critical mode to be on and off based on an error signal between the output voltage and the predetermined reference voltage, measuring ON time of a synchronous rectification switch operation of the first half-bridge circuit by measuring a time period between OFF timing of an active switch of the first half-bridge circuit and output of a differentiation signal generated by a differentiation circuit included in the bridgeless interleaved power factor correction circuit of the critical mode; and assigning the measured time to next ON time of the synchronous rectification switch operation of the second half-bridge circuit.
Osamu OHTAKE, Ryuichi FURUKOSHI
Filed: 22 Feb 22
Utility
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26 Jul 22
An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits.
Hideki Hayashi
Filed: 23 Mar 21
Utility
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14 Jul 22
A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region.
Taro KONDO
Filed: 12 Jan 21
Utility
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23 Jun 22
A DC-DC converter according to one or more embodiments is disclosed that may include: a drive voltage switching circuit of a drive circuit that drives a synchronous rectification MOS transistor.
Masaru NAKAMURA, Shinji ASO, Jianao YAO
Filed: 28 Sep 21
Utility
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9 Jun 22
An event processing method of a processor according to one or more embodiments may include detecting an event input, which notifies an occurrence of an event, detecting a wait event by an event input, changing a status from an execution status to a wait status and outputs a count start signal by an event wait instruction, and changes a status from the wait status to the execution status and outputs a count end signal by the detection of the wait event, incrementing a counter value from an initial value by output of the count start signal, and ends counting by output of the count end signal; and receiving and storing a count value of the timer counter by output of the count end signal.
Hitomi SHISHIDO, Daeun LEE, Kazuhiro MIMA
Filed: 24 Feb 22
Utility
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12 May 22
An analog-to-digital converter according to one or more embodiments is disclosed that converts an analog input to a digital converted value by repeating a conversion data generation operation by a conversion data generator, a potential generation operation by a capacitance DAC, and a comparison operation by a comparator for a resolution bit, the analog-to-digital converter. a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element whose characteristics are equal to those of the capacitance used in the capacitance DAC, and generates a comparator operation signal to allow the comparator to start the comparison operation.
Hideki HAYASHI
Filed: 29 Sep 21
Utility
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12 May 22
One or more embodiments of a successive approximation type analog-to-digital converter that converts an analog input into a digital conversion value and outputs the digital conversion value, may include: a capacitance DAC that generates a bit-by-bit potential based on an analog input; a comparator that compares the potential generated by the capacitance DAC, wherein the comparator is a memory cell rewriting type, the comparator includes a first stage current mirror type operational amplifier; and a second stage memory cell; a conversion data generator that generates conversion data of resolution bits based on a comparison result of the comparator; and a correction circuit that corrects an output error of the conversion data caused by an offset error of the comparator by adding or subtracting an offset correction value that is a fixed value, and outputs the conversion data as a digital conversion value.
Hideki HAYASHI
Filed: 29 Sep 21
Utility
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10 May 22
A multicore system according to one or more embodiments is disclosed, which may include processors that execute processing different from each other, a selector that selects one of the processors, a checker processor, a comparator that compares an external state of the processor selected by the selector with an external state of the checker processor, or compares an internal state of the processor selected by the selector with an internal state of the checker processor, and a controller that determines that the selected processor or the checker processor is abnormal in response to the external states or the internal states not matching each other based on comparison results obtained by the comparator.
Takanaga Yamazaki
Filed: 5 Jan 21
Utility
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21 Apr 22
An analog-digital conversion circuit is disclosed for comparing a comparison potential with a reference potential generated based on a reference power supply to convert a comparison potential to a digital value.
Hideki Hayashi
Filed: 28 Dec 21
Utility
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24 Mar 22
A semiconductor device is disclosed including a sub-layer with first conductivity type, a drift layer with first conductivity type, a base region with second conductivity type positioned on the drift layer, a source region in contact with the base region, a source electrode, a plurality of trenches, at least one of the trenches in contact with the drift layer, the base region, and the source region, a plurality of insulating regions, at least one of the insulating regions positioned inside of each trench, a plurality of gate electrodes, at least one of the gate electrodes positioned inside of each trench; and a plurality of field plates, at least one of the field plates electrically connected to the source electrode and positioned in the insulating region in the trench.
Taro KONDO
Filed: 1 Feb 21
Utility
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8 Feb 22
A data processing device according to one or more embodiment is disclosed.
Takanaga Yamazaki
Filed: 26 Jun 19
Utility
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8 Feb 22
A light emitting device (1) includes: three or more light emitting units (10, 20, 30) that individually include blue light emitting element, a wavelength range of the blue light emitting element accommodated in respective packages being different from each other.
Takaya Ueno, Hitoshi Murofushi
Filed: 30 Oct 17
Utility
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8 Feb 22
A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern.
Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
Filed: 23 Dec 19