22699 patents
Page 26 of 1135
Utility
Method and apparatus to provide an improved fail-safe system for critical and non-critical workloads of a computer-assisted or autonomous driving vehicle
19 Dec 23
Apparatuses, methods and storage medium associated with embedded computing, are disclosed herein.
Christopher Cormack, Matthew Curfman, Sebastien Hily
Filed: 17 Mar 20
Utility
Cryptographic protection of memory attached over interconnects
19 Dec 23
Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described.
Siddhartha Chhabra, Prashant Dewan
Filed: 19 Oct 21
Utility
0ice4cx0ibm2v12l69nng80fkyi9xgza1vs1v8k
19 Dec 23
Disclosed embodiments relate to accelerating multiplication of sparse matrices.
Dan Baum, Chen Koren, Elmoustapha Ould-Ahmed-Vall, Michael Espig, Christopher J. Hughes, Raanan Sade, Robert Valentine, Mark J. Charney, Alexander F. Heinecke
Filed: 24 Sep 21
Utility
iza3mfsmq56o7gv16r3aqaifv58rbky5323ecfhzv0dx05koz
19 Dec 23
Technologies for untrusted code execution include a computing device having a processor with sandbox support.
Mingwei Zhang, Mingqiu Sun, Ravi L. Sahita, Chunhui Zhang, Xiaoning Li
Filed: 2 Jul 21
Utility
2y242wiftklwp7e karcl6l4mhqw86g90
19 Dec 23
Techniques are provided for processing video frames in a process flow that includes first and second computation engines.
Pravin Chander Chandran, Raghavendra Bhat, Sean J. Lawrence
Filed: 12 Jun 20
Utility
43ouyalegeksr683zs9igfo8222ypi3ue0ns
19 Dec 23
Systems and methods are disclosed for providing non-lexical cues in synthesized speech.
Jessica M. Christian, Peter Graff, Crystal A. Nakatsu, Beth Ann Hockey
Filed: 23 Jun 22
Utility
76h9kbcavd7f999om5f9zaqs
19 Dec 23
Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described.
Dae-Woo Kim, Sujit Sharan
Filed: 13 Dec 18
Utility
21hcgzs2qe81a3kwew0jb okznhvzmt
19 Dec 23
Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein.
Sireesha Gogineni, Yi Xu, Yuhong Cai
Filed: 11 Oct 18
Utility
i91d3cqe8flfq2fn25y2rfgq4hc5jwddgmtopsdo6i
14 Dec 23
A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units.
JAMES VALERIO, VASANTH RANGANATHAN, JOYDEEP RAY, PRADEEP RAMANI
Filed: 6 Jul 23
Utility
9jct1si6f87f8rafvsvmomwhtb6rm3n0hww1y0wub kcfnlsjvnj
14 Dec 23
Deep neural networks (DNNs) with budding ensemble architectures may be trained using diversity loss.
Qutub Syed Sha, Neslihan Kose Cihangir, Rafael Rosales
Filed: 28 Aug 23
Utility
suw7irptuoiccb1n5k 65v8l8ep66p6
14 Dec 23
Methods and apparatus for optimization techniques for modular multiplication algorithms.
Erdinc OZTURK, Kirk S. YAP, Tomasz KANTECKI
Filed: 24 Aug 23
Utility
3t6qwff8ogkqvay2ncwhjdfpkk1s56isn6s6zct568
14 Dec 23
Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation.
Renu Patle, Hanmanthrao Patli, Rakesh Mehta, Hagay Spector, Ivan Herrera Mejia, Fylur Rahman Sathakathulla, Gowtham Raj Karnam, Mohsin Ali, Sahar Sharabi, Abraham Halevi Fraenkel, Eyal Pniel, Ehud Cohn, Raghav Ramesh Lakshmi, Altug Koker
Filed: 14 Jun 22
Utility
jrbhpgdjthewoyjcrupg9dtm313gb9hhsg613zv5os6out85fk4kvhkm4
14 Dec 23
In one embodiment, an apparatus comprises: a branch prediction circuit to predict whether a branch is to be taken; a fetch circuit, in a single fetch cycle, to send a first portion of a fetch region of instructions to a first decode cluster and send a second portion of the fetch region to the second decode cluster; the first decode cluster comprising a first plurality of decode circuits to decode one or more instructions in the first portion of the fetch region; and the second decode cluster comprising a second plurality of decode circuits to decode one or more other instructions in the second portion of the fetch region.
Mathew Lowes, Martin Licht, Jonathan Combs
Filed: 14 Jun 22
Utility
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14 Dec 23
An apparatus is described.
Ram KRISHNAMURTHY, Gregory K. CHEN, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL
Filed: 24 Aug 23
Utility
tpa8 mht75313bv0ifive3ull98l8bzn98x9i37yoxg
14 Dec 23
Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).
Niall D. MCDONNELL, Ambalavanar ARULAMBALAM, Te Khac MA, Surekha PERI, Pravin PATHAK, James CLEE, An YAN, Steven POLLOCK, Bruce RICHARDSON, Vijaya Bhaskar KOMMINENI, Abhinandan GUJJAR
Filed: 24 Aug 23
Utility
naxe aza2jbz4o8bf9xruynt30sg3hesglt46kgyp9kst
14 Dec 23
Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby.
BINATA BHATTACHARYYA, PAUL S. DIEFENBAUGH
Filed: 11 May 23
Utility
1rbr6olg9qgf2nedw853xtkwd96fekffss 7vy1a9bhnignt4
14 Dec 23
Some aspects of the present disclosure relate to an apparatus comprising interface circuitry and processor circuitry to write data bits to a memory, by applying a diffusion function on the data bits to calculate diffused data bits, calculating error correcting code (ECC) bits based on the data bits or based on the diffused data bits, applying a diffusion function on the ECC bits to calculate diffused ECC bits, storing the diffused ECC bits in an ECC portion of the memory, and storing the data bits or the diffused data bits in a data portion of the memory.
Sergej DEUTSCH, David M. DURHAM, Karanvir GREWAL, Raghunandan MAKARAM, Rajat AGARWAL, Christoph DOBRAUNIG, Krystian MATUSIEWICZ, Santosh GHOSH
Filed: 13 Jun 23
Utility
bkowq 4vkgtrxx363uwectxco5jvpinhjgvlu1iom86kaf
14 Dec 23
One embodiment provides an apparatus comprising a circuit board; an active interposer coupled with the circuit board via a debug package, and a graphics processor die coupled with the active interposer via the debug package.
Rakesh Mehta, Hanmanthrao Patli, Ivan Herrera Mejia, Raj Chandar Rasappan, Hagay Spector, Renu Patle, Fylur Rahman Sathakathulla, Ruchira Liyanage, Raju Kasturi, Fred Steinberg, Ananth Gopalakrishnan, Satish Venkatesan, Pradyumna Reddy Patnam, Suresh Pothukuchi, Tapan Ganpule, Atthar H. Mohammed, Altug Koker
Filed: 14 Jun 22
Utility
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14 Dec 23
A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided.
Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Barry E. Huntley, Baiju V. Patel, Deepak K. Gupta
Filed: 10 Aug 23
Utility
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14 Dec 23
One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.
Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
Filed: 25 Aug 23