22699 patents
Page 29 of 1135
Utility
Self-aligned Staggered Integrated Circuit Interconnect Features
7 Dec 23
Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization.
Miriam Reshotko, Elijah Karpov, Mark Anders, Gauri Auluck, Shakuntala Sundararajan, Michael Makowski, Caleb Barrett
Filed: 6 Jun 22
Utility
Selective Removal of Channel Bodies In Stacked Gate-all-around (Gaa) Device Structures
7 Dec 23
A semiconductor structure includes an upper device stacked over a lower device.
Munzarin F. Qayyum, Nicole K. Thomas, Jami A. Wiedemer, Jack T. Kavalieros, Marko Radosavljevic, Willy Rachmady, Cheng-Ying Huang, Rohit Galatage, Nitesh Kumar, Kai Loon Cheong, Venkata Vasiraju
Filed: 3 Jun 22
Utility
0bzg3flrocsd90ngawzqlpp6vbyxn8zcpll58jbiho
7 Dec 23
IC devices with transistors having angled gates, and related assemblies and methods, are disclosed herein.
Sagar Suthram, Abhishek A. Sharma, Wilfred Gomes, Tahir Ghani, Anand S. Murthy, Pushkar Sharad Ranade
Filed: 1 Jun 22
Utility
zo8ijxa6h2fpwu1sru3icwv7wc0n
7 Dec 23
An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device.
Willy Rachmady, Nitesh Kumar, Jami A. Wiedemer, Cheng-Ying Huang, Marko Radosavljevic, Mauro J. Kobrinsky, Patrick Morrow, Rohit Galatage, David N. Goldstein, Christopher J. Jezewski
Filed: 6 Jun 22
Utility
ilnh6mtnn0rc0nl6ed64id0f8lbn50xa417256rr qbp6sdcp8j9a
7 Dec 23
Disclosed herein are memory devices with gradient-doped control gate material, as well as related methods and devices.
Arkajit Roy Barman, Dimitrios Pavlopoulos, Dimitri Robert Kioussis, Srikant Jayanti, Jeremy Leroy Schroeder
Filed: 10 Dec 20
Utility
73l79qi314ce uah0zeol
7 Dec 23
In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer.
Srinivas V. Pietambaram, Kristof Darmawikarta, Tarek A. Ibrahim, Jeremy D. Ecton, Brandon Christian Marin, Gang Duan, Suddhasattwa Nad, Yi Yang, Benjamin T. Duong, Junxin Wang, Sameer R. Paital
Filed: 6 Jun 22
Utility
qjfbvg0hm2m55rfrode09 w6o4mqj8z65tb94sc8jdbkc7be
7 Dec 23
Systems, apparatus, articles of manufacture, and methods are disclosed for supports for internal hardware of electronic devices.
David Shia, Rick Canham, Eric W. Buddrius, Jeffory L. Smalley, John Beatty, Kenan Arik, Mohanraj Prabhugoud, Kirk Wheeler, Shelby Ferguson, Jorge Contreras Perez, Daniel Neumann, Ernesto Borboa Lizarraga
Filed: 16 Aug 23
Utility
86ycg1j gkt3x2h59eu3jqk1pvzdbcnd2ibhu3k3t0rk0v83illi
7 Dec 23
Microelectronic assemblies, and related devices and methods, are disclosed herein.
Aleksandar Aleksov, Johanna M. Swan
Filed: 17 Aug 23
Utility
xzjesh07j03glt9m6h37c3sqrpk00px0qj8a31m lheel
7 Dec 23
Embodiments disclosed herein include electronic packages.
Eng Huat GOH, Jiun Hann SIR, Chee Kheong YOON, Telesphor KAMGAING, Min Suet LIM, Kavitha NAGARAJAN, Chu Aun LIM
Filed: 6 Jun 22
Utility
fik6jhwune07yumlcg3p0sukdg2r8i
7 Dec 23
In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer.
Srinivas V. Pietambaram, Kristof Darmawikarta, Tarek A. Ibrahim, Jeremy D. Ecton, Brandon Christian Marin, Gang Duan, Suddhasattwa Nad, Yi Yang, Benjamin T. Duong, Junxin Wang, Sameer R. Paital
Filed: 6 Jun 22
Utility
e75t3nqblxqg402bclz88cq6xwarerm
7 Dec 23
Thermally conductive, electrically insulating materials and their manufacture on integrated circuit (IC) dies.
Jean-Pierre Njante, Telesphor Kamgaing
Filed: 2 Jun 22
Utility
qlp7 wawj22tlm36z4utyvqqb5nc30
7 Dec 23
A semiconductor structure includes a second device stacked over a first device.
Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Cheng-Ying Huang, Willy Rachmady, Rohit Galatage, Jami A. Wiedemer, David Bennett, Dincer Unluer, Venkata Aditya Addepalli
Filed: 3 Jun 22
Utility
k33z 9ez5wqvkkzwblb81qy
7 Dec 23
Embodiments disclosed herein include an electronic package.
Eng Huat GOH, Telesphor KAMGAING, Jooi Wah WONG, Min Suet LIM, Chee Kheong YOON, Kavitha NAGARAJAN, Chu Aun LIM
Filed: 6 Jun 22
Utility
6kwba139a1nlnyaf4ccqrb7b8e mfus99nv65tfdn27y3iy3
7 Dec 23
A substrate to printed circuit board (PCB) interconnect with liquid metal and surface pins.
Tin Poay Chuah, Jeff Ku, Min Suet Lim, Yew San Lim, Twan Sing Loo
Filed: 7 Jun 22
Utility
rq3rhroi3yvjlyx1k7ob5mvtwxv
7 Dec 23
Embodiments disclosed herein include electronic packages.
Min Suet LIM, Kavitha NAGARAJAN, Eng Huat GOH, Telesphor KAMGAING, Chee Kheong YOON, Jooi Wah WONG, Chu Aun LIM
Filed: 6 Jun 22
Utility
6rex7xav1q916z3hupjw6p761q0ewl5gu77fpann9h25
7 Dec 23
An integrated circuit structure includes a first device, and a second device laterally adjacent to the first device.
Willy Rachmady, Nitesh Kumar, Jami A. Wiedemer, Cheng-Ying Huang, Marko Radosavljevic, Mauro J. Kobrinsky, Patrick Morrow, Rohit Galatage, David N. Goldstein, Christopher J. Jezewski
Filed: 6 Jun 22
Utility
lc6cp1i5ttzefwpumalh8lvsns3hjq2
7 Dec 23
Embodiments disclosed herein include package substrates.
Jooi Wah WONG, Eng Huat GOH, Telesphor KAMGAING, Chee Kheong YOON, Min Suet LIM, Kavitha NAGARAJAN, Chu Aun LIM
Filed: 6 Jun 22
Utility
0xuszlx0k2iblj5umpt7wjiltsx11vndqplqn2vxqun9 rx
7 Dec 23
Techniques and mechanisms for using multiple delay line circuits to detect a change to the frequency of a periodic signal.
Terry Remple
Filed: 7 Jun 22
Utility
kyxb0v8h3hwr1n3wsyt7k10wj s1v9qul62suidyq
7 Dec 23
Embodiments disclosed herein include electronic packages.
Eng Huat GOH, Telesphor KAMGAING, Chee Kheong YOON, Jooi Wah WONG, Min Suet LIM, Kavitha NAGARAJAN, Chu Aun LIM
Filed: 6 Jun 22
Utility
eciav5ukefsnagnq4gl3530mry6tycmdf279t0jvimmu9u2dcc9zn
7 Dec 23
Techniques for sharing private data objects in a trusted execution environment using a distributed ledger are described.
Mic Bowman, Andrea Miele, James P. Held, Anand Rajan
Filed: 16 Aug 23