22699 patents
Page 30 of 1135
Utility
Technologies for Transparent Function As a Service Arbitration for Edge Systems
7 Dec 23
Technologies for function as a service (FaaS) arbitration include an edge gateway, multiple endpoint devices, and multiple service providers.
Francesc Guim Bernat, Ned Smith, Kshitij Doshi, Alexander Bachmutsky, Suraj Prabhakaran
Filed: 16 Aug 23
Utility
Protecting Data Transfer Between a Secure Application and Networked Devices
7 Dec 23
An apparatus to facilitate protecting data transfer between a secure application and networked devices is disclosed.
Luis Kida, Reshma Lal
Filed: 22 Aug 23
Utility
ayqx88s8favb42fjxwvg06jqwntb0087pjlzu7mqom5
7 Dec 23
A magnetic grounding technique implements a magnet assembly.
Ying Ern Ho, Boon Ping Koh, Ya Yeing Lo, Luqman Al-Hakim Mohd Nasran, Ameera Wahida Solikhudin
Filed: 23 Aug 23
Utility
ckw c1jk3q9iaqj6uhh9zzipjiu03172v4
7 Dec 23
Techniques and mechanisms for accessing memory arrays which are formed in a back end of line (BEOL) of an integrated circuit (IC) die.
Pulkit Jain, Juan Alzate Vinasco, Liqiong Wei, Ozdemir Akin, Fatih Hamzaoglu
Filed: 7 Jun 22
Utility
brvegdvoz7gwrwqz7uaxxjb2gpa35jhrd49i ttw
7 Dec 23
A next generation vehicle-to-everything (NGV) station (STA) operating as an initiating station (ISTA) for performing non-trigger-based NGV ranging may encode an NGV ranging null-data packet (NDP) announcement (NGV NDPA) frame for transmission to a responding station (RSTA) to initiate the non-trigger-based NGV ranging.
Qinghua Li, Bahareh Sadeghi, Jonathan Segev, Xiaogang Chen, Thomas J. Kenney, Robert J. Stacey
Filed: 6 Dec 21
Utility
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7 Dec 23
An integrated circuit includes a first cryptographic module that enables debugging of the first cryptographic module and a second cryptographic module that disables debugging of the second cryptographic module.
Richard Fant
Filed: 22 Aug 23
Utility
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7 Dec 23
Various embodiments herein provide techniques for wireless communication on New Radio unlicensed (NR-U) spectrum.
Carlos H. Aldana, Salvatore Talarico, Yingyang Li, Yongjun Kwak
Filed: 21 Aug 23
Utility
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7 Dec 23
Described herein are various embodiments of reducing dynamic power consumption within a processor device.
Mohammed Tameem, Altug Koker, Kiran C. Veernapu, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, Travis T. Schluessler, Jonathan Kennedy
Filed: 1 Jun 23
Utility
71hyu0bo3my8hqwck9ewk0fadk hw7ltwcpi4emkp5782gq
7 Dec 23
Various embodiments herein provide techniques for reference signal time difference (RSTD) measurement based on the New Radio (NR) positioning reference signal (PRS).
Rui Huang, Zhibin Yu, Qiming Li, Andrey Chervyakov
Filed: 10 May 23
Utility
14hiottq8ma76k8itv1ptlhtgo4ik9gvdsln86fik
7 Dec 23
A processor includes a register to store an encoded pointer for a memory address within a first memory allocation of a plurality of memory allocations in a memory region of a memory.
David M. Durham, Michael LeMay, Sergej Deutsch, Dan Baum
Filed: 30 Sep 22
Utility
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7 Dec 23
Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels.
Venkata Reddy Sanamreddy, Adithya Kumar Swaminathan, Chakravarti Bheemisetti
Filed: 2 Jun 22
Utility
bumlsdx x6ebkn6exg0ou8h6xrxtpqcm62lxm5n953pdtlf8pq1
7 Dec 23
A memory device may include a level shifter circuit that drives multiples half latch circuits.
William K. Waller, Sarang Agrawal
Filed: 2 Jun 22
Utility
birj9ksc4pp2et0ai184bokjkb13tkxqjs79s6ao8gt6s htc76
7 Dec 23
A network interface device for implementing scheduling for time sensitive networking includes a network interface device comprising media access control (MAC) circuitry, including a priority router to parse a packet payload to determine a priority value; determine a corresponding traffic class based on the priority value from the packet payload; and route the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and a packet router to: retrieve a packet payload from the plurality of traffic class-based packet buffers based on the traffic class; and place the packet payload in a queue for a direct memory access (DMA) circuitry to store the packet payload in main memory.
Kishore Kasichainula
Filed: 16 Aug 23
Utility
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7 Dec 23
In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form.
Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amitai Armon, Uzi Sarel
Filed: 30 May 23
Utility
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7 Dec 23
Methods, apparatuses, and computer readable media for report identification and power control for multi-device wireless sensing in a wireless network are disclosed.
Cheng Chen, Carlos Cordeiro, Claudio Da Silva, Bahareh Sadeghi
Filed: 16 Aug 23
Utility
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7 Dec 23
One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.
Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha, Nadathur Rajagopalan Satish, Jeremy Bottleson, Farshad Akhbari, Altug Koker, Narayan Srinivasa, Dukhwan Kim, Sara S. Baghsorkhi, Justin E. Gottschlich, Feng Chen, Elmoustapha Ould-Ahmed-Vall, Kevin Nealis, Xiaoming Chen, Anbang Yao
Filed: 14 Jun 23
Utility
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7 Dec 23
Embodiments disclosed herein include a printed circuit board (PCB).
Min Suet LIM, Tin Poay CHUAH, Yew San LIM, Jeff KU, Twan Sing LOO, Poh Boon KHOO, Jiun Hann SIR
Filed: 7 Jun 22
Utility
kovo3t5a6rm79enmk0utqvn8mq0ink79nbbl
7 Dec 23
Activations (e.g., output activations) or weights of intermediate layers of deep neural networks (DNNs) can be pruned to increase sparsity and reduce the amount of computation required for performing the computations in the layers or subsequent layers.
Soumendu Kumar Ghosh, Shamik Kundu, Arnab Raha, Deepak Abraham Mathaikutty
Filed: 22 Aug 23
Utility
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7 Dec 23
Embodiments disclosed herein include package substrates.
Eng Huat GOH, Chee Kheong YOON, Telesphor KAMGAING, Jooi Wah WONG, Min Suet LIM, Kavitha NAGARAJAN, Chan Kim LEE, Chu Aun LIM
Filed: 6 Jun 22
Utility
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7 Dec 23
In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.
Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nir Rosenzweig, Yoni Aizik
Filed: 24 Aug 23