10908 patents
Page 57 of 546
Utility
Precise longitudinal monitoring of memory operations
4 Jul 23
A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem.
Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
Filed: 21 Apr 20
Utility
Methods and apparatus to detect and annotate backedges in a dataflow graph
4 Jul 23
Disclosed examples to detect and annotate backedges in data-flow graphs include: a characteristic detector to store a node characteristic identifier in memory in association with a first node of a dataflow graph; a characteristic comparator to compare the node characteristic identifier with a reference criterion; and a backedge identifier generator to generate a backedge identifier indicative of a backedge between the first node and a second node of the dataflow graph based on the comparison, the memory to store the backedge identifier in association with a connection arc between the first and second nodes.
Kermin E. ChoFleming, Jr., Jesmin Jahan Tithi, Joshua Cranmer, Suresh Srinivasan
Filed: 7 Jun 21
Utility
ies0xxns7t4iplndjjvjxvkd28npghcpb6a1hnwflie4tt1qo0kgzwo43fg
4 Jul 23
One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register.
Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin, Kamal Sinha
Filed: 26 Jul 21
Utility
nqjx69en93ua5lym6fcrodde5but3rg1exfm 3dfwzolnh9dv80onpvikr
4 Jul 23
Embodiments of systems, methods, and apparatuses for heterogeneous computing are described.
Rajesh M. Sankaran, Gilbert Neiger, Narayan Ranganathan, Stephen R. Van Doren, Joseph Nuzman, Niall D. McDonnell, Michael A. O'Hanlon, Lokpraveen B. Mosur, Tracy Garrett Drysdale, Eriko Nurvitadhi, Asit K. Mishra, Ganesh Venkatesh, Deborah T. Marr, Nicholas P. Carter, Jonathan D. Pearce, Edward T. Grochowski, Richard J. Greco, Robert Valentine, Jesus Corbal, Thomas D. Fletcher, Dennis R. Bradford, Dwight P. Manley, Mark J. Charney, Jeffrey J. Cook, Paul Caprioli, Koichi Yamada, Kent D. Glossop, David B. Sheffield
Filed: 21 Jul 21
Utility
roqrxaly2pwqaolvzw1mw1ejgbehgakur302nbndos1ws
4 Jul 23
A system for generating a robustness score for hardware components, nodes, and clusters of nodes in a computing infrastructure is provided.
Rita H. Wouhaybi, Patricia M. Mwove Shaffer, Aline C. Kenfack Sadate, Lidia Warnes
Filed: 25 Sep 21
Utility
p8h56ynk7eypixd7wdhfsscfbgofxngguwmw
4 Jul 23
Embodiments are directed to aggregate GHASH-based message authentication code (MAC) over multiple cachelines with incremental updates.
David M. Durham, Karanvir S. Grewal, Sergej Deutsch, Michael E. Kounavis
Filed: 3 Mar 22
Utility
oc7tqm5wb24fifykdw0wij
4 Jul 23
Technologies for managing memory on a compute device are disclosed.
Xiaoyong Du
Filed: 31 Aug 21
Utility
7vwaxrn6bx6xbtlpz6k8ykz2eoq8mo6rp214jc0dfwios
4 Jul 23
System and method for prefetching pointer-referenced data.
Sreenivas Subramoney, Stanislav Shwartsman, Anant Nori, Shankar Balachandran, Elad Shtiegmann, Vineeth Mekkat, Manjunath Shevgoor, Sourabh Alurkar
Filed: 2 Aug 21
Utility
fdcwaxt1s8vup52zvzp5g809x6
4 Jul 23
An apparatus and method for tagged memory management.
Ron Gabor, Enrico Perla, Raanan Sade, Igor Yanover, Tomer Stark, Joseph Nuzman
Filed: 27 Dec 19
Utility
hc05rwmb38jrng66tvwn7z2f95kw87
4 Jul 23
Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers.
Balaji Parthasarathy, Ramamurthy Krithivas, Bradley A. Burres, Pawel Szymanski, Yi-Feng Liu
Filed: 19 Mar 21
Utility
cxnqyvxz6nm6873zscwnqqhh8jerhb1e2sltb 8j
4 Jul 23
An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed.
Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
Filed: 24 Dec 21
Utility
yl5333ihjeozvm7g1hb5olcl 12uiev8wrr3tqepqqubu
4 Jul 23
A computer platform is disclosed.
Bharat Pillilli, David W. Palmer, Nikola Radovanovic
Filed: 23 Jun 21
Utility
8do5lig40yz8pjicgu852z0oht2hm7kk69ap okpnijix0by8v25kzaidm
4 Jul 23
Methods, systems, and articles of manufacture to autonomously select data structures are disclosed.
Justin Gottschlich
Filed: 23 Dec 19
Utility
670jc0jl5xnwf0jnzndnhfedv6f137pj2 uhepfr
4 Jul 23
Embodiments are disclosed for emulation of graphics processing unit instructions.
Konstantin Levit-Gurevich, Michael Berezalsky, Noam Itzhaki, Arik Narkis, Orr Goldman
Filed: 24 Sep 21
Utility
xemyo2t9kt agmdyu6guj
4 Jul 23
Technology for a display source controller is described.
Nausheen Ansari
Filed: 28 Feb 22
Utility
gcc9dzu24 5r0hmluoiccbuptbpp7023ts5z6x6tp0cyausv
4 Jul 23
A stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element.
Chuanzhao Yu, Qiang Li, David Newman
Filed: 30 Mar 18
Utility
vfyejq6fa2po 8mwyre8233azskbkh287w39inntkmtm1i5dsm
4 Jul 23
Embodiments disclosed herein include electronic packages and methods of forming such packages.
Suddhasattwa Nad, Jeremy Ecton, Bai Nie, Rahul Manepalli, Marcel Wall
Filed: 25 Mar 19
Utility
bs2h3ueywfyizbq3bomkedtqm41xmzk936erpdnrmuo59hka9b3agtv6a814
27 Jun 23
Hearing protection and communication apparatus using vibration sensors are disclosed.
Willem M. Beltman, Hector A. Cordourier Maruri, Paulo Lopez Meyer, Jonathan Huang
Filed: 17 May 21
Utility
z18nlz zkhnwyjnbqwupvpgq8c
27 Jun 23
In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric.
Lakshminarayana Pappu, Robert P. Adler, R. Selvakumar Raja Gopal
Filed: 2 Nov 17
Utility
dr6khqqv8fsffyrm6j3psesywzx0q2zue34u4akqx
27 Jun 23
Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
Sankaran M. Menon, Vasudev Bibikar, P. Reddy Sahajananda, Sunghyun Koh, Naveendran Balasingam
Filed: 15 Apr 21