10908 patents
Page 58 of 546
Utility
Methods and apparatus to trigger calibration of a sensor node using machine learning
27 Jun 23
Methods, apparatus, systems and articles of manufacture to trigger calibration of a sensor node using machine learning are disclosed.
Yatish Mishra, Mats Agerstam, Mateo Guzman, Sindhu Pandian, Shubhangi Rajasekhar, Pranav Sanghadia, Troy Willes
Filed: 8 Nov 21
Utility
Multi-level CPU high current protection
27 Jun 23
Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described.
Efraim Rotem, Nir Rosenzweig, Doron Rajwan, Alon Naveh, Eliezer Weissmann
Filed: 28 Mar 22
Utility
ef36jhrm1lludo3mh80mtqh8koh39eazi o0x
27 Jun 23
Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack.
Shravan Kumar Belagal Math, Noor Mubeen, Harinarayanan Seshadri
Filed: 14 Jun 21
Utility
a5db09nckuwmqr5likt0x wmalhq10e1j19apsp
27 Jun 23
Technologies for an accelerator interface over Ethernet are disclosed.
Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming
Filed: 29 Sep 17
Utility
exym1ki46php9x8b08y1hm
27 Jun 23
System and techniques for an internet-of-things device blank are described herein.
Atif Hussein, Trina Ward, Patricia Robb
Filed: 7 Mar 22
Utility
vzry thgkwsos44z7a9j2rmaktobbdx8dczgchyrm67bm
27 Jun 23
In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory.
Nitin N. Garegrat, Tony L. Werner, Jeff DelChiaro, Michael Rotzin, Robert T. Rhoades, Ujwal Basavaraj Sajjanar, Anne Q. Ye
Filed: 29 Aug 19
Utility
j41r0 9y96pg7uteep7ywcdvrqphayqhmzxayws5e9d2ipp
27 Jun 23
Technologies for hybrid field-programmable gate array (FPGA) application-specific integrated circuit (ASIC) code acceleration are described.
Ned Smith, Changzheng Wei, Songwu Shen, Ziye Yang, Junyuan Wang, Weigang Li, Wenqian Yu
Filed: 20 Apr 22
Utility
dozeaxu5f7i8wwaa8gp975yvfv5dlmldw8pr58
27 Jun 23
Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks.
Gaurav Porwal, Subhankar Panda, John G. Holm
Filed: 1 Nov 21
Utility
tynr3rn m6cprssg1jdoyoqss051vq234w27cldkimkoabs233bi1
27 Jun 23
Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media.
Chetan Chauhan, Wei Wu, Rajesh Sundaram, Shigeki Tomishima
Filed: 18 Nov 21
Utility
du4b525be8212k9y13hgtz9dxj0t
27 Jun 23
Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
Filed: 13 May 21
Utility
kr0w6p9vo0nvlxe42qijrqunzeggrpcttb3cmsj45w248y7
27 Jun 23
A method is described.
Joseph D. Tarango, Randal Eike, Michael Allison, Eric Hoffman
Filed: 27 Mar 20
Utility
imk6oyifiqc6av29guhy 8xa44uq
27 Jun 23
Implementations describe providing isolation in virtualized systems using trust domains.
Ravi L. Sahita, Baiju V. Patel, Barry E. Huntley, Gilbert Neiger, Hormuzd M. Khosravi, Ido Ouziel, David M. Durham, Ioannis T. Schoinas, Siddhartha Chhabra, Carlos V. Rozas, Gideon Gerzon
Filed: 15 Sep 17
Utility
6xtg8p5kcgfx67s pd8oz9qr
27 Jun 23
System and techniques for multi-tenant cryptographic memory isolation are described herein.
Shay Gueron, Siddhartha Chhabra, Nadav Bonen
Filed: 14 Sep 20
Utility
h64oaz8zoq6jf4ynkyzeeahg4wel5khhi6o4z70evfvjubr03 izar
27 Jun 23
An example apparatus for video frame segmentation includes a receiver to receive a current video frame to be segmented.
Amir Goren, Noam Elron, Noam Levy
Filed: 25 Jun 20
Utility
19u6lxu90ucj4bs5whwvdhn94l7weqvkdpsgk3iz7lkfhrld77xck49
27 Jun 23
An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor.
Devan Burke, Adam T. Lake, Jeffery S. Boles, John H. Feit, Karthik Vaidyanathan, Abhishek R. Appu, Joydeep Ray, Subramaniam Maiyuran, Altug Koker, Balaji Vembu, Murali Ramadoss, Prasoonkumar Surti, Eric J. Hoekstra, Gabor Liktor, Jonathan Kennedy, Slawomir Grajewski, Elmoustapha Ould-Ahmed-Vall
Filed: 2 Feb 22
Utility
7l6arqdsz3ijgvs7sqrws6149txjn8cdvq
27 Jun 23
In one embodiment, an apparatus comprises a communication interface and a processor.
Marcos Emanuel Carranza, Lakshmi N. Talluru, Cesar I. Martinez Spessot, Mateo Guzman, Sebastian M. Salomon, Mats G. Agerstam
Filed: 21 May 21
Utility
6poh8nm9w7w36xta1upmb2zkkl h4
27 Jun 23
Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays.
Travis Schluessler, Abhishek Venkatesh, John Gierach, Tomer Bar-On, Devan Burke
Filed: 30 Aug 21
Utility
g0dngk764ryf1c97tlqlgd3xz58u3odlm3bc181osr711jcfkv5gd1x
27 Jun 23
A memory device with internal row hammer mitigation couples to a memory controller.
Bill Nale, Christopher E. Cox
Filed: 3 Mar 22
Utility
zb2ph1cb6q1nrz7feivbifl3enk496id6wggvggaudcb8rzgy
27 Jun 23
Techniques are provided for mobile platform based detection and prevention (or mitigation) of hearing loss.
Vikas Mishra, Raghavendra S. Hebbalalu, Anand V. Bodas, Kalyan Muthukumar
Filed: 26 Mar 20
Utility
hbhwny9c3wcc7asrfg4d9zafytiopmsdj27gvcncgs8ykpdv
27 Jun 23
Embodiments disclosed herein include composite dies and methods of forming such composite dies.
Vipul Mehta, Yiqun Bai, Ziyin Lin, John Decker, Yan Li
Filed: 30 Jul 19