10908 patents
Page 64 of 546
Utility
Methods and apparatus to optimize workflows
23 May 23
Methods, apparatus, systems and articles of manufacture are disclosed that optimize workflows.
Thijs Metsch, Joseph Butler, Mohammad Mejbah Ul Alam, Justin Gottschlich
Filed: 25 Jun 19
Utility
High-performance input-output devices supporting scalable virtualization
23 May 23
Techniques for scalable virtualization of an Input/Output (I/O) device are described.
Utkarsh Y. Kakaiya, Rajesh Sankaran, Sanjay Kumar, Kun Tian, Philip Lantz
Filed: 29 Jun 21
Utility
7k7ann8l41lt4yh8ora4m
23 May 23
A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry.
Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz, Sreenivas Subramoney
Filed: 24 Jan 22
Utility
1i399pl6gwddyoshy5kkuy5rn1l6nptot9nic2mx2y088ss73
23 May 23
Disclosed embodiments relate to a cache line eviction algorithm.
Neha Gholkar, Akhilesh Kumar
Filed: 26 Nov 19
Utility
6zkcbrn0rfoekkn6rgjs1g6luwtn ro7lk1phwwo4vl8
23 May 23
An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing.
Ron Gabor, Enrico Perla, Raanan Sade, Igor Yanover, Tomer Stark
Filed: 28 Dec 19
Utility
0se1zngy3mzzzvf2ukfn blty4f18hshluvopn
23 May 23
A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol.
Debendra Das Sharma, Anil Vasudevan, David Harriman
Filed: 20 Jan 21
Utility
tfty8tca1eecr5a0x9swt p4nwaejeum0g
23 May 23
In one example an apparatus comprises a memory and a processor to create, from a first deep neural network (DNN) model, a first plurality of DNN models, generate a first set of adversarial examples that are misclassified by the first plurality of deep neural network (DNN) models, determine a first set of activation path differentials between the first plurality of adversarial examples, generate, from the first set of activation path differentials, at least one composite adversarial example which incorporates at least one intersecting critical path that is shared between at least two adversarial examples in the first set of adversarial examples, and use the at least one composite adversarial example to generate a set of inputs for a subsequent training iteration of the DNN model.
Michael Kounavis, Antonios Papadimitriou, Anindya Sankar Paul, Micah Sheller, Li Chen, Cory Cornelius, Brandon Edwards
Filed: 22 Mar 19
Utility
5u2dvrrri73ffu8pl 7p6u9fsx4xqpk4vvepuzmsroddu
23 May 23
An example apparatus for selecting priors includes a training set receiver to receive a training dataset.
Konstantin Rodyushkin, Alexander Bovyrin
Filed: 5 Feb 18
Utility
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23 May 23
Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH).
Carsten Benthin, Sven Woop, Ingo Wald
Filed: 29 Mar 22
Utility
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23 May 23
Apparatus and method for processing virtual graphics processor telemetry data based on quanta.
Ankur Shah, Matthew Callaway, Vivek Garg, Rajeev K. Nalawadi, James Varga
Filed: 12 Apr 22
Utility
y908dmrbxkurs3sdg4bfebemcxnv31oyz8l5w2aahidek 0eply9npvoh
23 May 23
Methods and apparatus to transition between 2D and 3D renderings of augmented reality content are disclosed.
Pete Denman, John Sherry, Glen J. Anderson, Benjamin Bair, Rebecca Chierichetti, Ankur Agrawal, Meng Shi
Filed: 29 Jul 22
Utility
1xdkgfbt8ou8hhnlws1 10qf76v68x2dui5hz
23 May 23
Computers for supporting multiple virtual reality (VR) display devices and related methods are described herein.
Anshuman Thakur, DongHo Hong, Karthik Veeramani, Arvind Tomar, Brent Insko, Atsuo Kuwahara, Zhengmin Li
Filed: 1 Mar 19
Utility
falp2l6cgyci0wht8e0vcd uxuxuupocby46y1am
23 May 23
Embodiments herein relate to systems, apparatuses, or processes directed to facilitating increased clock speeds on a substrate by lowering the impedance of traces that provide clock signals to components such as DRAM.
Rogelio Alfonso Moreyra Gonzalez, Jose Angel Ramos Martinez, James McCall
Filed: 22 Mar 19
Utility
o3sw8jm1dcqu7navssd4b4dgsme7pq368k
23 May 23
Error correction values for a memory device include row error correction values and column error correction values for the same memory array.
Jawad B. Khan, Richard L. Coulson, Zion S. Kwok, Ravi H. Motwani
Filed: 23 Mar 20
Utility
w3c1gpylfqm03tpw8pfjcbk3hj78r45qlhg
23 May 23
An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.
Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
Filed: 26 Jul 21
Utility
d3pa05kgkgqahyb2lm6cgzfs8ag8vifpmlei43vigzktwj9x2h118afrf
23 May 23
Embodiments disclosed herein include electronic packages and methods of forming such packages.
Suddhasattwa Nad, Rahul Manepalli
Filed: 25 Mar 19
Utility
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23 May 23
Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package.
Hyoung Il Kim, Yi Xu, Florence Pon
Filed: 17 Jan 19
Utility
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23 May 23
An IC package, comprising a first IC component comprising a first interconnect on a first surface thereof; a second IC component comprising a second interconnect on a second surface thereof.
Kelly Lofgreen, Chandra Mohan Jha, Krishna Vasanth Valavala
Filed: 29 Mar 19
Utility
71uq0gul2rvpwue76 p8aqpj75cphgob0iqtv5unyjogmm6qqsrt93fj7el1
23 May 23
An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer.
Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Amruthavalli Pallavi Alur, Debendra Mallik
Filed: 12 Mar 21
Utility
gqfvqi1u0jfdn73tspbxg3gyvpre3czvxf o5aq10nb9f9ree2u85
23 May 23
Embodiments disclosed herein include electronic packages for PoINT architectures.
Robert Sankman, Robert May
Filed: 18 Mar 19