134 patents
Page 7 of 7
Utility
System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
23 Mar 20
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second.
Vipin Tiwari, Nhan Do, Hieu Van Tran
Filed: 19 Dec 17
Utility
Twin bit non-volatile memory cells with floating gates in substrate trenches
23 Mar 20
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate.
Chunming Wang, Andy Liu, Xian Liu, Leo Xing, Melvin Diao, Nhan Do
Filed: 14 Oct 18
Utility
dujo834c2n3315zco b0o58kvto
9 Mar 20
A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance.
Xiaozhou Qian, Kai Man Yue, Guang Yan Luo
Filed: 29 Aug 18
Utility
j5xopp5n2yp79lcge9iuynzgi6oev70ukub6 d822q52
9 Mar 20
A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output.
Vipin Tiwari, Nhan Do
Filed: 1 Jul 18
Utility
x2ccjma042u44et7f v7
2 Mar 20
A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver.
Vipin Tiwari, Hieu Van Tran, Nhan Do, Mark Reiten
Filed: 20 Jun 18
Utility
tekkumepyj4ux2yplfa7iziockv1xi49o5r39pnq
2 Mar 20
A memory array with memory cells arranged in rows and columns.
Vipin Tiwari, Nhan Do
Filed: 20 Aug 18
Utility
8gdpi7wp7laidqn9a48undw3iwrckf2rlz3
27 Jan 20
An improved low-power sense amplifier for use in a flash memory system is disclosed.
Xiaozhou Qiang, Xiao Yan Pi, Kai Man Yue, Li Fang Bian
Filed: 29 Aug 18
Utility
uvqonkc8l7pgld8rgry9uxgi0a1ys9h6tt21gknqx3nrbjacpahk0oc
13 Jan 20
Apparatus, and an associated method, for enhancing security and preventing hacking of a flash memory device.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 12 Oct 17
Utility
rupcix79hnj4pbhzjj3ac3 yr4cm4je2sv7er7hcahdmjuj97g8tjd1z6
30 Dec 19
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network.
Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
Filed: 22 Jul 18
Utility
8tmr18eo4voynypqlamdkpw
23 Dec 19
A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current.
Vipin Tiwari, Nhan Do, Hieu Van Tran
Filed: 30 Sep 18
Utility
clowlip3917lcdo8s8qy5w4ezqek4sud1y0anzr7ll0 mjwt
4 Nov 19
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins.
Feng Zhou, Jinho Kim, Xian Liu, Serguei Jourba, Catherine Decobert, Nhan Do
Filed: 18 Apr 18
Utility
yj6j73olhi79 5nfkrpfy
28 Oct 19
An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
Hieu Van Tran, Anh Ly, Thuan Vu, Hung Quoc Nguyen
Filed: 24 Aug 17
Utility
8zpq0a4s3j4zqf1xfm33rez5vg0x5tk6c3fceh5gfni2ate
28 Oct 19
A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 16 Apr 19
Utility
y9injcgngiwyfwk917hwq1x
14 Oct 19
Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed.
Hieu Van Tran, Vipin Tiwari, Nhan Do
Filed: 24 May 18