805 patents
Page 4 of 41
Utility
Waveform construction using interpolation of data points
10 Oct 23
A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data.
John Stonick, Michael W. Lynch, Dino Toffolon, Ayal Shoval
Filed: 26 Jun 20
Utility
Color Graph Reduction on a Line of Connected Structures
5 Oct 23
The present disclosure describes systems and methods for assigning nodes in a circuit design to layers.
Xuerong DING, Yuli XUE, Chen GAO
Filed: 28 Mar 23
Utility
System and method for auditing a graph-based API
3 Oct 23
A method for auditing a graph-based API includes obtaining a structure describing object types of the API and fields of the object types.
Shane Edward Wilton, Kavin Subramanyam, Nathaniel Robert Heydt
Filed: 5 Aug 20
Utility
High speed, low hardware footprint waveform
3 Oct 23
A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA.
Arturo Salz, Ching-Ping Chou, Jean-Philippe Colrat, Sébastien Roger Delerse, Luc Francois Vidal, Arnold Mbotchak
Filed: 28 Jan 21
Utility
Fin patterning to reduce fin collapse and transistor leakage
3 Oct 23
At least one fin structure may be created on a silicon substrate.
Victor Moroz, Xi-Wei Lin
Filed: 2 Dec 20
Utility
Static Timing Analysis of Multi-die Three-dimensional Integrated Circuits
28 Sep 23
A system performs timing analysis of three-dimensional integrated circuits (3DICs).
Subramanyam Sripada, Song Chen
Filed: 25 Mar 22
Utility
Reducing Spurious Write Operations In a Memory Device
28 Sep 23
A memory device includes bitcells connected to wordlines and bitlines, and driver circuitry that updates the bitcells.
Shishir KUMAR, Vinay KUMAR
Filed: 21 Mar 23
Utility
Coherent observability and controllability of overlaid clock and data propagation in emulation and prototyping
19 Sep 23
The independent claims of this patent signify a concise description of embodiments.
Alex Rabinovitch, Bojan Mihajlovic, Xavier Guerin, Manish Shroff
Filed: 25 Sep 19
Utility
Method and system for custom model definition of analog defects in an integrated circuit
19 Sep 23
A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design.
Mayukh Bhattacharya, Michael Durr, Mira Tzakova, Beatrice Solignac, Rayson Yam
Filed: 20 Apr 21
Utility
Net-based wafer inspection
19 Sep 23
A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC).
Ankush Bharati Oberai, Rajesh Ramesh Sahani
Filed: 17 Dec 20
Utility
Aging-resistant Schmitt receiver circuit
19 Sep 23
A receiver circuit may include a first stage and a second stage.
Rahul Gupta, Nitin Bansal, Akhil Thotli, Manoj Kumar Reddy Puli
Filed: 15 Oct 21
Utility
Inverse lithography and machine learning for mask synthesis
19 Sep 23
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed.
Amyn A. Poonawala, Jason Jiale Shu, Thomas Christopher Cecil
Filed: 23 Nov 20
Utility
Detecting shared rescources and coupling factors
12 Sep 23
A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design.
Shivakumar Shankar Chonnad, Radu Horia Iacob, Vladimir Litovtchenko
Filed: 28 Dec 21
Utility
Diversifying stimulus generation in constrained random simulation by learning distribution history
12 Sep 23
Techniques and systems for generating constrained random stimuli during functional verification of a design under verification (DUV) are described.
Malay K. Ganai
Filed: 29 Jan 20
Utility
Optical interconnections for hybrid testing using automated testing equipment
5 Sep 23
A hybrid optical-electrical automated testing equipment (ATE) system can implement a workpress assembly that can interface with a device under test (DUT) and a load board that holds the DUT during testing, analysis, and calibration.
Steven William Keck, Crispin Cruz Mapagay, Mark Stenholm
Filed: 30 Jul 20
Utility
Compact opto-electric probe
5 Sep 23
Described are various configurations for performing efficient optical and electrical testing of an opto-electrical device using a compact opto-electrical probe.
Molly Piels, Anand Ramaswamy, Brandon Gomez
Filed: 16 Dec 21
Utility
Mask rule checking for curvilinear masks for electronic circuits
5 Sep 23
A system performs mask rule checks (MRC) for curvilinear shapes.
Thomas Christopher Cecil
Filed: 23 Dec 22
Utility
Throughput efficient Reed-Solomon forward error correction decoding
5 Sep 23
A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit; an error locator and error evaluator polynomial calculator circuit; an error location and error value calculator circuit; an error counter; and an error corrector circuit to correct the errors in the first codeword and the second codeword based on error counts and the error magnitudes computed by an error evaluator circuit.
Venugopal Santhanam, Aman Mishra
Filed: 29 Jun 22
Utility
On-the-fly Multi-bit Flip Flop Generation
31 Aug 23
On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.
Deepak D. SHERLEKAR, Basannagouda REDDY, Shanie GEORGE
Filed: 8 May 23
Utility
Memory efficient and scalable approach to stimulus (waveform) reading
22 Aug 23
Embodiments relate to reading signals from a stimulus file produced by an emulator into a data store.
Anup Kumar Sultania, Ajay Singh Bisht, Mark W. Brown
Filed: 7 Apr 21