805 patents
Page 5 of 41
Utility
System and method to process a virtual partition cell injected into a hierarchical integrated circuit design
22 Aug 23
Aspects described herein relate to physical verification of a design of an integrated circuit to be manufactured on a semiconductor die.
Yulan Wang
Filed: 25 May 21
Utility
Visual representation to assess quality of input stimulus in transistor-level circuits
22 Aug 23
In one aspect, a transistor-level description of a circuit is accessed, where the circuit includes a plurality of transistors.
Mayukh Bhattacharya, Aleksandrs Krjukovs, Chih-Ping Antony Fan
Filed: 9 Nov 21
Utility
Circuit layout verification
22 Aug 23
A system, method, and computer readable medium with instructions for verifying an original layout are disclosed.
Jinsik Yun, Mark Daniel Pogers, Jonathan Calvin White, Chiu-Yu Ku, Danny Chang, Lihhsing Ke
Filed: 2 Jun 21
Utility
Interface Level-shifter Dual-rail Memory Architecture
17 Aug 23
A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry.
Harold PILO, Shishir KUMAR, Anurag GARG, Peter LEE, John Edward BARTH
Filed: 8 Feb 23
Utility
Transforming Local Wire Thru Resistances into Global Distributed Resistances
17 Aug 23
A method for transient analysis of a memory module circuit, the method including: determining port to port resistances between terminals of internal circuits of a plurality of leaf cells of a netlist representing the memory module circuit; generating a plurality of equivalent networks corresponding to the internal circuits of the leaf cells, the equivalent networks being connected to each other; promoting the equivalent networks of the leaf cells to a hierarchical level above the leaf cells in the netlist representing the memory module circuit; shorting one or more terminals of each of the leaf cells to a central node of a corresponding one of the equivalent networks; and performing the transient analysis of the leaf cells of the netlist representing the memory module circuit.
Jeffrey Herbert, John Edward Barth, JR., Matthew Christopher Lanahan
Filed: 8 Feb 23
Utility
Waveform based reconstruction for emulation
15 Aug 23
A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete.
Gagan Vishal Jain, Johnson Adaikalasamy, Alexander John Wakefield, Ritesh Mittal, Solaiman Rahim, Olivier Coudert
Filed: 11 Nov 21
Utility
Under test pin location driven simultaneous signal grouping and pin assignment
15 Aug 23
A method includes generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplex data rate (XDR) of the first signal pin and the second signal pin.
Yu Yang, Jianfeng Huang, Shih-Ying Liu
Filed: 29 Sep 21
Utility
Transforming a Logical Netlist into a Hierarchical Parasitic Netlist
10 Aug 23
A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device.
Jeffrey C. HERBERT, Matthew Christopher LANAHAN, John Edward BARTH
Filed: 9 Feb 22
Utility
Correlating Open Source Component Matching Results Using Different Scanning Techniques
10 Aug 23
A processing device receives a request to analyze the file hierarchy comprising the plurality of components and sends respective commands to a plurality of matching services.
Douglas Albert Brown, Damon Alexander Weinstein, Jagat Prakashchandra Parekh
Filed: 8 Feb 22
Utility
Mask synthesis using design guided offsets
8 Aug 23
Aspects described herein relate to mask synthesis using design guided offsets.
Thomas Cecil, Kevin Hooker
Filed: 25 Jun 21
Utility
Fast Waveform Capture with Low Hardware Footprint Enabling Full Visibility
3 Aug 23
A method of generating waveforms of a circuit design in a hardware emulation system, includes, capturing, using a first block of the system, input signals at each k*d emulation cycle, wherein k and d are integers and k≥0 and d>0; capturing, using the first logic block at each (k*d+i) cycle, value of each input signal determined to have changed relative to a previous emulation cycle, wherein 0<i<d; capturing, using a second logic block, outputs of sequential elements at each k*w*d emulation cycle, wherein w is an integer greater than zero; capturing, using the second logic block, at each (k*w*d+j*d) emulation cycle, outputs of each sequential element that is determined to have changed relative to cycle (k*w*d+(j−1)*d), wherein j is an integer and wherein 0<j<w; and generating waveforms for the signals based on the captured input signals and captured values of the sequential elements.
Olivier Sallenave, Jeremy Ozog, Olivier Coudert, Thiago Martins, Cedric Thepenier
Filed: 27 Jan 23
Utility
Memory Instance Reconfiguration Using Super Leaf Cells
3 Aug 23
A system and method for characterizing a memory instance.
John Edward BARTH, Jeffrey C. HERBERT, Matthew Christopher LANAHAN
Filed: 3 Feb 22
Utility
Automated method to check electrostatic discharge effect on a victim device
1 Aug 23
Some aspects of this disclosure are directed to an automated method to check electrostatic discharge (ESD) effect on a victim device.
Jeffrey Ellis Byrd, Peter C. de Jong, Herman Luijmes
Filed: 22 Nov 21
Utility
Automatic sequential retry on compilation failure
25 Jul 23
A compilation system accesses a compilation operations that can be used by a compiler to compile a design under test (DUT).
Guillaume Jean Baptiste Desplechain
Filed: 3 Dec 21
Utility
Fabrication technique for forming ultra-high density integrated circuit components
25 Jul 23
A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided.
Xi-Wei Lin, Victor Moroz
Filed: 9 Jul 21
Utility
Three-dimensional mask simulations based on feature images
18 Jul 23
A layout geometry of a lithographic mask is received.
Peng Liu
Filed: 31 Aug 21
Utility
Automated balanced global clock tree synthesis in multi level physical hierarchy
18 Jul 23
Embodiments provide for building a global clock tree.
Ashima Sahil Dabare, Sanjiv Mathur, Anusha Reddy Sindhwala, Prakasha Karkada Holla, Sivakumar Arulanantham, Srinivasan Krishnamurthy, Chun-Cheng Chi, Shih-Pin Hung
Filed: 16 Jun 21
Utility
Hardware based cyclic redundancy check (CRC) re-calculator for timestamped frames over a data bus
18 Jul 23
A method and a system for correcting cyclic redundancy check (CRC) for a frame with last bytes changed are provided.
Jishnu De, Jaspreet Singh Gambhir, Jitendra Puri
Filed: 30 Dec 21
Utility
Optical temperature measurements in photonic circuits
11 Jul 23
Temperature measurements of photonic circuit components may be performed optically, exploiting a temperature-dependent spectral property of the photonic device to be monitored itself, or of a separate optical temperature sensor placed in its vicinity.
Chris Barnard, John Parker
Filed: 5 Oct 20
Utility
Photodetector with sequential asymmetric-width waveguides
11 Jul 23
Described are various configurations of optical structures having asymmetric-width waveguides.
Jonathan Edgar Roth, Jared Bauters, Erik Johan Norberg
Filed: 29 Jun 22