12220 patents
Page 2 of 611
Utility
Latch type sense amplifier
9 Jan 24
A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit.
Hua-Hsin Yu, Hung-Jen Liao, Cheng-Hung Lee, Hau-Tai Shieh
Filed: 30 Aug 21
Utility
Double-sided stacked DTC structure
9 Jan 24
In some embodiments, the present disclosure relates to an integrated circuit (IC), including a first insulating layer which includes a first metal interconnect structure stacked above a bottom die.
Ming Chyi Liu
Filed: 26 Aug 21
Utility
Circuits and methods for a noise shaping analog to digital converter
9 Jan 24
Systems and methods are provided for analog-to-digital conversion (ADC).
Martin Kinyua, Eric Soenen
Filed: 12 Apr 22
Utility
Interposer routing structure and semiconductor package
9 Jan 24
An interposer routing structure includes a first trace layer, a bump layer, a second trace layer and a third trace layer.
Sheng-Fan Yang, Hao-Yu Tung, Hung-Yi Chang, Wei-Chiao Wang, Yi-Tzeng Lin
Filed: 5 May 23
Utility
Multi-bit memory storage device
9 Jan 24
A FeFET configured as a 2-bit storage device that includes a gate stack including a ferroelectric layer over a semiconductor substrate; and the ferroelectric layer includes dipoles; and a first set of dipoles at the first end of the ferroelectric layer has a first polarization; and a second set of dipoles at the second end of the ferroelectric layer has a second polarization, the first and second polarizations of the corresponding first and second sets of dipoles representing storage of 2 bits, wherein a first bit of the 2-bit storage device being configured to be read by application of a read voltage to the source region and a do-not-disturb voltage to the drain region; and a second bit of the 2-bit storage device being configured to be read by application of the do-not-disturb voltage to the source region and the read voltage to the drain region.
Meng-Han Lin, Chia-En Huang, Han-Jong Chia, Martin Liu, Sai-Hooi Yeong, Yih Wang
Filed: 15 Dec 22
Utility
Embedded ferroelectric memory cell
9 Jan 24
The present disclosure relates to an integrated chip structure.
Tzu-Yu Chen, Kuo-Chi Tu, Wen-Ting Chu, Yong-Shiuan Tsair
Filed: 18 Jul 22
Utility
Method for fabricating a semiconductor device
9 Jan 24
A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant.
Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
Filed: 22 Jun 20
Utility
Back-side deep trench isolation structure for image sensor
9 Jan 24
The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation.
Yu-Hung Cheng, Chun-Tsung Kuo, Jiech-Fun Lu, Min-Ying Tsai, Chiao-Chun Hsu, Ching I Li
Filed: 11 Sep 20
Utility
Semiconductor package device and semiconductor wiring substrate thereof
9 Jan 24
A semiconductor wiring substrate includes a first circuit layer, a second circuit layer and a first dielectric layer.
Sheng-Fan Yang, Wei-Chiao Wang, Yi-Tzeng Lin
Filed: 29 Aug 22
Utility
Bond pad structure for bonding improvement
9 Jan 24
A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed.
Chin-Wei Liang, Sheng-Chau Chen, Hsun-Chung Kuang, Sheng-Chan Li
Filed: 13 Nov 20
Utility
Semiconductor device and manufacturing method thereof
9 Jan 24
A semiconductor device and a manufacturing method thereof are provided.
Georgios Vellianitis
Filed: 29 Jun 22
Utility
Polysilicon resistor structures
9 Jan 24
The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes.
Meng-Han Lin, Wen-Tuo Huang, Yong-Shiuan Tsair
Filed: 21 Jul 22
Utility
Semiconductor device structure and methods of forming the same
9 Jan 24
A semiconductor device structure, along with methods of forming such, are described.
Jhon Jhy Liaw
Filed: 15 Sep 21
Utility
Control gate strap layout to improve a word line etch process window
9 Jan 24
Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines.
Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yong-Shiuan Tsair, Chia-Sheng Lin, Shih Kuang Yang
Filed: 31 Aug 21
Utility
Nanostructured channel regions for semiconductor devices
9 Jan 24
A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed.
Chansyun David Yang, Keh-Jeng Chang, Chan-Lon Yang, Perng-Fei Yuh
Filed: 28 May 21
Utility
Integrated circuit with nanosheet transistors with robust gate oxide
9 Jan 24
A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors.
Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Kuan-Lun Cheng
Filed: 8 Jul 21
Utility
Thin-film transistors and method for manufacturing the same
9 Jan 24
A transistor includes a gate electrode, a gate dielectric located over the gate electrode, a channel layer that includes an oxide semiconductor material and that is located over the gate dielectric, a buffer located to cover at least a portion of the channel layer, and source/drain contacts disposed on the buffer.
Georgios Vellianitis, Marcus Johannes Henricus Van Dal, Gerben Doornbos
Filed: 19 Apr 21
Utility
Failsafe input/output electrostatic discharge protection with diodes
9 Jan 24
Systems and methods are provided for fail-safe protection of circuitry from electrostatic discharge due through input and output connections.
Tzu-Heng Chang, Hsin-Yu Chen
Filed: 24 Sep 21
Utility
Clock gating circuit and method of operating the same
9 Jan 24
A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor.
Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang, Chi-Lin Liu
Filed: 13 Dec 22
Utility
Memory cell structure
9 Jan 24
A memory device including a rectangular shaped via for at least one Vss node connection.
Jhon Jhy Liaw
Filed: 5 Feb 21