12220 patents
Page 4 of 611
Utility
Semiconductor device and method of manufacturing the same
2 Jan 24
In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area.
Meng-Han Lin, Chih-Ren Hsieh, Ching-Wen Chan
Filed: 3 Jan 22
Utility
Memory device, integrated circuit device and method
2 Jan 24
A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller.
Meng-Han Lin, Sai-Hooi Yeong, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
Filed: 19 Jan 23
Utility
Magnetic random access memory and manufacturing method thereof
2 Jan 24
In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed.
Shy-Jay Lin, Chwen Yu, William J. Gallagher
Filed: 26 Jul 21
Utility
Integrated circuit fin structure manufacturing method
2 Jan 24
A method of manufacturing an IC structure includes forming a first plurality of fins extending in a first direction on a substrate, a second plurality of fins extending adjacent to the first plurality of fins, a third plurality of fins extending adjacent to the second plurality of fins, and a fourth plurality of fins extending adjacent to the third plurality of fins.
Po-Hsiang Huang, Fong-Yuan Chang, Clement Hsingjen Wann, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien, Chia-Ming Hsu
Filed: 13 Dec 22
Utility
Stressing algorithm for solving cell-to-cell variations in phase change memory
2 Jan 24
A process is provided to trim PCRAM cells to have consistent programming curves.
Jau-Yi Wu
Filed: 10 Aug 22
Utility
MRAM stacks and memory devices
2 Jan 24
Memory stacks, memory devices and method of forming the same are provided.
Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
Filed: 29 Jul 22
Utility
FinFET device and method of forming same
2 Jan 24
A semiconductor device a method of forming the same are provided.
Bo-Cyuan Lu, Tai-Chun Huang, Chih-Tang Peng, Chi On Chui
Filed: 13 Jan 21
Utility
Method for forming semiconductor package
2 Jan 24
A method of forming a semiconductor package is provided.
Chin-Hua Wang, Po-Yao Lin, Feng-Cheng Hsu, Shin-Puu Jeng, Wen-Yi Lin, Shu-Shen Yeh
Filed: 14 May 21
Utility
Package structure and method of manufacturing the same
2 Jan 24
A package structure includes a semiconductor die and a first redistribution circuit structure.
Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
Filed: 29 Oct 21
Utility
Semiconductor devices with backside routing and method of forming same
2 Jan 24
In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
Filed: 18 Dec 20
Utility
Sidewall spacer to reduce bond pad necking and/or redistribution layer necking
2 Jan 24
In some embodiments, an integrated chip (IC) is provided.
Alexander Kalnitsky, Kong-Beng Thei
Filed: 21 Jul 22
Utility
3D trench capacitor for integrated passive devices
2 Jan 24
Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same.
Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
Filed: 20 Dec 21
Utility
Semiconductor device including source/drain contact having height below gate stack
2 Jan 24
A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
Filed: 10 Feb 23
Utility
Work function design to increase density of nanosheet devices
2 Jan 24
In some embodiments, the present disclosure relates to an integrated chip.
Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
Filed: 21 Feb 22
Utility
Nanostructure with various widths
2 Jan 24
A semiconductor structures and a method for forming the same are provided.
Hsiao-Han Liu, Chih-Hao Wang, Kuo-Cheng Chiang, Shi-Ning Ju, Kuan-Lun Cheng
Filed: 10 Jun 22
Utility
Wave guide filter for semiconductor imaging devices
2 Jan 24
In some embodiments, an image sensor is provided.
Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
Filed: 19 Jan 22
Utility
Gate structures for semiconductor devices
2 Jan 24
The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed.
Chung-Liang Cheng, Chun-I Wu, Huang-Lin Chao
Filed: 28 Jun 21
Utility
Method of manufacturing a semiconductor device
2 Jan 24
In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.
Ming-Wen Hsiao, Chun-Yen Tai, Yen-Hsin Liu, Ming-Jhih Kuo, Ming-Feng Shieh
Filed: 23 Apr 21
Utility
Stacked multi-gate structure and methods of fabricating the same
2 Jan 24
A semiconductor device according to the present disclosure includes a stack of first channel layers and first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively.
Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng
Filed: 27 May 21
Utility
Semiconductor device and manufacturing method thereof
2 Jan 24
In a method of manufacturing a semiconductor device, a fin structure having a bottom part and an upper part on the bottom part is formed over a substrate.
Jiun Shiung Wu, Guan-Jie Shen
Filed: 9 Aug 21