12220 patents
Page 5 of 611
Utility
Method for forming semiconductor device structure with nanowires
2 Jan 24
Structures and formation methods of a semiconductor device structure are provided.
Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
Filed: 30 Aug 21
Utility
Self-aligned spacers for multi-gate devices and method of fabrication thereof
2 Jan 24
A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature.
Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
Filed: 11 Apr 22
Utility
System and method of verifying slanted layout components
2 Jan 24
Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component.
Yuan-Te Hou, Min-Yuan Tsai
Filed: 6 Aug 21
Utility
Read circuit for magnetic tunnel junction (MTJ) memory
2 Jan 24
In some embodiments, the present application provides a memory device.
Gaurav Gupta, Zhiqiang Wu
Filed: 19 May 22
Utility
Buffer control of multiple memory banks
2 Jan 24
Disclosed herein are related to operating a memory system including memory banks and buffers.
Shih-LIen Linus Lu
Filed: 28 Jul 22
Utility
Fine line patterning methods
2 Jan 24
A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
Filed: 31 Jan 22
Utility
Semiconductor substrate bonding tool and methods of operation
2 Jan 24
A bonding tool includes a gas supply line that may extend directly between valves associated with one or more gas supply tanks and a processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks.
Yen-Hao Huang, Chun-Yi Chen, I-Shi Wang, Yin-Tun Chou, Yuan-Hsin Chi, Sheng-Yuan Lin
Filed: 26 May 21
Utility
Semiconductor package and method of fabricating semiconductor package
2 Jan 24
A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate.
Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
Filed: 26 Feb 21
Utility
Through-substrate-via with reentrant profile
2 Jan 24
The present disclosure relates an integrated chip.
Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
Filed: 17 Feb 21
Utility
Integrated circuit conductive line arrangement for circuit structures, and method
2 Jan 24
A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type.
Chih-Yu Lai, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien
Filed: 27 Aug 21
Utility
Package structure with solder resist underlayer for warpage control and method of manufacturing the same
2 Jan 24
A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer.
Ting-Chen Tseng, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
Filed: 18 Dec 19
Utility
High ESD immunity field-effect device and manufacturing method thereof
2 Jan 24
An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein.
Yu-Hung Yeh
Filed: 3 Mar 21
Utility
Semiconductor device and method for manufacturing the same
2 Jan 24
A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer.
Hsin-Fu Lin, Tsung-Hao Yeh, Chih-Wei Hung
Filed: 13 May 21
Utility
High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device
2 Jan 24
Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device.
Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
Filed: 31 Aug 21
Utility
Contact plugs and methods forming same
2 Jan 24
A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD).
Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
Filed: 22 Feb 21
Utility
Methods of semiconductor device fabrication including growing epitaxial features using different carrier gases
2 Jan 24
A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures.
Feng-Ching Chu, Chung-Chi Wen, Wei-Yuan Lu, Feng-Cheng Yang, Yen-Ming Chen
Filed: 12 Nov 20
Utility
Circuit and method for high voltage tolerant ESD protection
2 Jan 24
In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed.
Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
Filed: 22 Apr 22
Utility
Conductor scheme selection and track planning for mixed-diagonal-manhattan routing
2 Jan 24
The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing.
Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
Filed: 3 Oct 22
Utility
Electromigration evaluation methodology with consideration of current distribution
2 Jan 24
The present disclosure provides a method for evaluating a heat sensitive structure.
Hsien Yu-Tseng, Wei-Ming Chen
Filed: 14 Oct 20
Utility
Optical sensor and methods of making the same
2 Jan 24
Optical sensors and their making methods are described herein.
You-Cheng Jhang, Han-Zong Pan, Wei-Ding Wu, Jiu-Chun Weng, Hsin-Yu Chen, Cheng-San Chou, Chin-Min Lin
Filed: 23 Nov 22