849 patents
Page 39 of 43
Utility
Semiconductor device and control method of semiconductor device
6 Jan 20
A semiconductor device includes a reference voltage generation circuit configured to generate reference voltages Va and Vb capable of adjusting a primary temperature characteristic, and an oscillation circuit configured to output an oscillation signal using the reference voltages Va and Vb, in which the oscillation circuit includes a frequency/current conversion circuit that is driven by the reference voltage Va and outputs a current Ie in accordance with a frequency of a feedback signal, a control voltage generation circuit configured to generate a control voltage in accordance with a potential difference between a voltage in accordance with the current Ie and the reference voltage Vb, a voltage control oscillation circuit configured to output the oscillation signal having a frequency in accordance with the control voltage, and a frequency division circuit configured to divide a frequency of the oscillation signal and output the resulting signal as the feedback signal.
Guoqiang Zhang, Kosuke Yayama
Filed: 21 Mar 18
Utility
Semiconductor device
6 Jan 20
In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part.
Kazuaki Kurooka, Yoshihiro Funato
Filed: 9 Jul 18
Utility
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30 Dec 19
A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain.
Yukitoshi Tsuboi, Hideo Nagano, Hiroshi Nagaoka, Yusuke Matsunaga, Yutaka Igaku, Naotaka Kubota
Filed: 31 Oct 17
Utility
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30 Dec 19
Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition.
Hiromichi Yamada, Akihiro Yamate, Yoichi Yuyama
Filed: 2 Aug 18
Utility
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30 Dec 19
In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion.
Atsushi Nishikizawa, Tadatoshi Danno
Filed: 25 Sep 17
Utility
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30 Dec 19
A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows.
Tamotsu Ogata
Filed: 12 Nov 18
Utility
6yh1acimg9uvz8yoiofj4b2sz0opwx71psltmjvwci03xhmwt7qnj
30 Dec 19
A semiconductor device includes a voltage measurement unit that measures an output voltage of a battery, a current measurement unit that measures a discharge current of the battery; and a controller that determines, in a first measurement mode, whether to employ a first discharge current as a power calculation current based on a difference between the first and a second discharge current, the second discharge current being the discharge current measured by the current measurement unit before the first discharge current is measured, in which the controller estimates an internal resistance of the battery based on the power calculation current and the output voltage measured in the first measurement mode and the discharge current and the output voltage measured in a second measurement mode, and calculates, based on the internal resistance that is estimated, a maximum power amount that can be output by the battery in the second measurement mode.
Hidekazu Nagato
Filed: 2 Oct 18
Utility
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23 Dec 19
A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.
Shinji Tanaka, Yuichiro Ishii, Masaki Tsukude, Yoshikazu Saito
Filed: 20 Dec 18
Utility
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23 Dec 19
A performance of a semiconductor device is improved.
Yukihiro Sato, Toshinori Kiyohara
Filed: 22 Mar 18
Utility
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23 Dec 19
A semiconductor device which provides improved reliability.
Yoshiaki Sato, Shuuichi Kariyazaki, Kazuyuki Nakagawa
Filed: 18 Nov 17
Utility
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23 Dec 19
A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate.
Yoshihiko Shimanuki
Filed: 27 May 18
Utility
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23 Dec 19
Susumu Hirata
Filed: 30 Jan 18
Utility
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16 Dec 19
A semiconductor storage device provided can increase a write margin and suppress increase of a chip area.
Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
Filed: 18 Apr 18
Utility
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16 Dec 19
In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region.
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Kengo Masuda
Filed: 3 Jan 19
Utility
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16 Dec 19
On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region.
Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
Filed: 4 Sep 17
Utility
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16 Dec 19
A semiconductor device has a peak value storage register, a threshold value storage register, a peak determination circuit, and an end timing determination circuit.
Takashi Otsuji
Filed: 5 Jul 17
Utility
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16 Dec 19
To improve identification precision of a motor constant that controls a motor by vector control.
Takahito Ishino
Filed: 2 Aug 18
Utility
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16 Dec 19
An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.
Hiroyuki Hamasaki, Atsushi Nakamura, Manabu Koike, Hideaki Kido, Nobuyasu Kanekawa
Filed: 16 Sep 18
Utility
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9 Dec 19
A magnetometer includes a diamond sensor, an excitation light source, a diamond sensor case, and a photodiode.
Yuji Hatano, Takashi Yoshino
Filed: 13 Feb 17
Utility
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9 Dec 19
When the same processing as initial training is executed to cope with fluctuation in the timing of a signal, the performance of a semiconductor device utilizing the relevant memory is degraded.
Takayuki Hotaruhara
Filed: 5 Feb 18