22699 patents
Page 13 of 1135
Utility
Package Heaters for Cold Temperature Operation and Method
4 Jan 24
A semiconductor package comprises two or more dies including at least one integrated circuit.
Ganesh Kondapuram, Chetan Rawal, Kevin Connolly, Robert Anderson
Filed: 30 Jun 22
Utility
Microelectronic Assemblies Including Stacked Dies Coupled by a Through Dielectric Via
4 Jan 24
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods.
Stephen Morein, Ravindranath Vithal Mahajan, Prashant Majhi
Filed: 30 Jun 22
Utility
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4 Jan 24
Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices.
Kristof Darmawikarta, Srinivas Pietambaram, Benjamin Duong, Haobo Chen
Filed: 30 Jun 22
Utility
q1dr6454z6z0vn32x7v9ju b0gj4vy2xz6eebc4hfeolm3msa2yzlsv5
4 Jan 24
An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA.
Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
Filed: 14 Sep 23
Utility
nt1ffi3fpo1i7fcxh 1g7uzubd8shpq4
4 Jan 24
A substrate package comprises a substrate comprised of buildup layers.
Suddhasattwa Nad, Jeremy D. Ecton, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jason Steill, Yi Yang, Marcel Arlan Wall
Filed: 1 Jul 22
Utility
xhv1lq3nh1mhm58s z3m0embkj
4 Jan 24
Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory.
Abhishek Sharma, Tahir Ghani, Wilfred Gomes, Anand Murthy
Filed: 1 Jul 22
Utility
itczwnq2cssqef4pcvvpsuci78ifrsm66xwf0ar6f53
4 Jan 24
Embodiments herein relate to systems, apparatuses, techniques, or processes for stiffeners for a surface of a package substrate, where the stiffeners provide EMI/RFI shielding for signal traces or other electrical routings within the package, and in particular for traces at a surface of the package such as microstrip routings.
Telesphor KAMGAING, Chu Aun LIM, Eng Huat GOH, Min Suet LIM, Kavitha NAGARAJAN, Jooi Wah WONG, Chee Kheong YOON
Filed: 29 Jun 22
Utility
tquotcnb92nc9fz95w0vgb1d1kvglpf1k6otlb831 ow
4 Jan 24
Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein.
Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
Filed: 1 Jul 22
Utility
kcrwuxx5s54q45q usugpiurx3xrkczhhwbv6htiw
4 Jan 24
A semiconductor package including: a package substrate including a base die disposed on a top surface of the package substrate, the base die including a plurality of electrical components disposed on a top surface of the base die, the plurality of electrical components including a first electrical component configured adjacent to a second electrical component, wherein the first electrical component and the second electrical component have an asymmetric form-factor; and a stiffener including: a stiffener main portion, wherein the stiffener main portion is affixed to the top surface of the package substrate and configured at least partially surrounding the base die; and a stiffener extension portion configured to extend from the stiffener main portion to be disposed at least partially over the top surface of the base die adjacent to the first electrical component and the second electrical component.
Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
Filed: 4 Jul 22
Utility
joigw65ekp221a5nyg4he0h2zhuabi8dj4fj0d jszg4m2xlg
4 Jan 24
An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region.
Cheng-Ying Huang, Kai Loon Cheong, Pooja Nath, Susmita Ghose, Rambert Nahm, Natalie Briggs, Charles C. Kuo, Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Jack T. Kavalieros, Thoe Michaelos, David Kohen
Filed: 30 Jun 22
Utility
o89wvnf6nnav2a4kcbef w0ynbcbnzejrmfpmdg
4 Jan 24
A semiconductor package includes a silicon die including a first die surface coupled to a package substrate, a second die surface opposite to the first die surface, and at least one die sidewall orthogonal to the first die surface and the second die surface, and a mold layer including a first mold surface, a second mold surface opposite to the first mold surface, and at least one mold sidewall orthogonal to the first mold surface and the second mold surface, the at least one mold sidewall being disposed along the at least one die sidewall, and the mold layer further including a power conductive corridor extending from the first mold surface and coupled to the package substrate through the first mold surface.
Seok Ling LIM, Jenny Shio Yin ONG, Bok Eng CHEAH, Jackson Chung Peng KONG, Kooi Chi OOI
Filed: 4 Jul 22
Utility
5mampee4s04p5pk6qo2ukdr6240rocqf423sblhkr9efbwh5hjc242hwlh90
4 Jan 24
Techniques and mechanisms for providing epitaxial structures of an integrated circuit (IC).
Abhishek Sharma, Anand Murthy, Tahir Ghani, Wilfred Gomes
Filed: 1 Jul 22
Utility
s35yqinyjhtxuj 6gg635su3vgg44vak
4 Jan 24
Embodiments disclosed herein include transistors and methods of forming transistors.
Chelsey DOROW, Kevin P. O'BRIEN, Sudarat LEE, Ande KITAMURA, Ashish Verma PENUMATCHA, Carl H. NAYLOR, Kirby MAXEY, Chia-Ching LIN, Scott B. CLENDENNING, Uygar E. AVCI
Filed: 29 Jun 22
Utility
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4 Jan 24
Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality.
Steven Hsu, Amit Agarwal, Simeon Realov, Mark Anders, Ram Krishnamurthy
Filed: 1 Jul 22
Utility
p5vdumbnduk1fnm8dy2u1ycwtrypcmbwyacsywf1zvg410709pv4tqq
4 Jan 24
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for electrically coupling components of a transistor structure together in order to perform a voltage contrast test to determine opens and shorts within the transistor structure.
Xiao WEN, Dipto THAKURTA, Sairam SUBRAMANIAN, Manish SHARMA
Filed: 30 Jun 22
Utility
tmxiqqj hggna1etc116uqhj9zi6w08p
4 Jan 24
Embodiments disclosed herein include a transistor and methods of making a transistor.
Walter CASPER, IV, Sudipto NASKAR, Marci Kahiehie Mi Hyon KANG, Weimin HAN, Vivek THIRTHA, Jianqiang LIN
Filed: 29 Jun 22
Utility
io781qcjwprcig xzo1jgls3
4 Jan 24
Embodiments disclosed herein include package substrates and methods of forming such substrates.
Suddhasattawa NAD, Rahul N. MANEPALLI, Gang DUAN, Srinivas V. PIETAMBARAM, Yi YANG, Marcel WALL, Darko GRUJICIC, Haobo CHEN, Aaron GARELICK
Filed: 29 Jun 22
Utility
pxh8x8jarh578lv69cq4di1zc8eex4sgoet7u1ehci6ks6viwejqov9sw
4 Jan 24
Substrate assemblies having adhesion promotor layers and related methods are disclosed.
Yi Yang, Srinivas Pietambaram, Darko Grujicic, Marcel Wall, Suddhasattwa Nad, Ala Omer, Brian P. Balch, Wei Wei
Filed: 30 Jun 22
Utility
jg9os50lun5zrepfa9ozxgvf4wzdc77ym0vjy6jzhew1twm7bph15yp
4 Jan 24
Structures having vertical keeper or power gate for backside power delivery are described.
Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Cory WEBER, Rishabh MEHANDRU, Wilfred GOMES, Sagar SUTHRAM
Filed: 30 Jun 22
Utility
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4 Jan 24
Embodiments herein relate to systems, apparatuses, or processes directed to fabricating passive circuits on a surface of a BEOL of a package, for example on a C4 connection layer of the BEOL.
Qiang YU, Georgios C. DOGIAMIS, Gwang-Soo KIM, Ibukunoluwa MOMSON, Ali FARID, Said RAMI
Filed: 29 Jun 22