22699 patents
Page 14 of 1135
Utility
Integrated Circuit Structures Having Ultra-high Conductivity Global Routing
4 Jan 24
Structures having ultra-high conductivity global routing are described.
Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Sagar SUTHRAM, Pushkar RANADE, Wilfred GOMES, Rishabh MEHANDRU, Cory WEBER
Filed: 30 Jun 22
Utility
Contact Architecture for 2D Stacked Nanoribbon Transistor
4 Jan 24
Embodiments disclosed herein include transistors and methods of forming transistors.
Ashish Verma PENUMATCHA, Kevin P. O'BRIEN, Kirby MAXEY, Carl H. NAYLOR, Chelsey DOROW, Uygar E. AVCI, Matthew V. METZ, Sudarat LEE, Chia-Ching LIN, Sean T. MA
Filed: 30 Jun 22
Utility
amychggmt 5avlspdf7mk0jjb1e9f17cqbp3ajq1aoufzxuy76a5
4 Jan 24
A device is disclosed.
Aaron LILAK, Rishabh MEHANDRU, Willy RACHMADY, Harold KENNEL, Tahir GHANI
Filed: 13 Sep 23
Utility
1dol92y57ixl10d2b338ne69a7hlitpilrqzj0ghwokq97aj7
4 Jan 24
An apparatus, system, and method for multi-frequency oscillator control are provided.
Timo Huusari, Mohamed A. Abdelmoneum, Brent R. Carlton, Somnath Kundu, Hao Luo, Sarah Shahraini, Jason Mix, Eduardo Alban
Filed: 30 Jun 22
Utility
6ylquue3bx49k62zg9piqqhklornmr1vbo ggop5y7tdmf1l
4 Jan 24
A method and apparatus for automatic gain control (AGC).
Gregory CHANCE, Peter PAWLIUK
Filed: 30 Jun 22
Utility
ia05i4mxcc28xhh5xkgc7jrx0z1309no6wb8m0q8g35zmrqqgkd2u
4 Jan 24
A radio frequency front-end (RF-FE) device with a reconfigurable common-mode feedback control.
Martin CLARA, Giacomo CASCIO, Erfan GHADERI, Marc Jan Georges TIEBOUT
Filed: 29 Jun 22
Utility
nf2pcv9cc9aq147ex7cc959vbxc5qmwlgbg65lrrt6oi9gv6rz2kwe9fw
4 Jan 24
Structures having vertical transistors are described.
Abhishek Anil SHARMA, Rishabh MEHANDRU, Sagar SUTHRAM, Cory WEBER, Tahir GHANI, Anand S. MURTHY, Pushkar RANADE, Wilfred GOMES
Filed: 30 Jun 22
Utility
g9wnohi7i 7yglgr9qbh
4 Jan 24
Embodiments herein relate to systems, apparatuses, or processes for packages that include transceivers that are at least partly positioned underneath a waveguide launcher array to decrease the maximum signal transmission time between the transceiver and the waveguide launcher array.
Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Nada SEKELJIC
Filed: 29 Jun 22
Utility
iyzehkb2f1pt2jlmp9mumq1kf99btw95433n4ci3umz
4 Jan 24
The present disclosure is directed to a printed circuit board having a composite upper surface with a first section of a first-type of printed circuit board and a second section of a second-type of printed circuit board, for which the first section of the first-type of printed circuit board and the second section of the second-type of printed circuit board are coupled, respectively, to at least one device that is configured to abridge the first and second sections of the composite upper surface.
Howe Yin LOO, Tin Poay CHUAH, Jenny Shio Yin ONG, Chee Min LOH, Bok Eng CHEAH, Jackson Chung Peng KONG, Seok Ling LIM, Kooi Chi OOI
Filed: 4 Jul 22
Utility
fgc3hskxlnvqckx425izsycxm3soqy43pfeuxmka0xt9cd0j 0p93f
4 Jan 24
A multi-step analog-to-digital converter (ADC).
Michael FULDE, Harneet KHURANA, Matteo CAMPONESCHI, Patrizia GRECO, Christian LINDHOLM, Martin CLARA, Giacomo CASCIO
Filed: 29 Jun 22
Utility
ycjoh4obyfmw yl8xncbcs3m0428p3nvnr
4 Jan 24
System and techniques for device-specific connections in an information centric network (ICN) are described herein.
Rustam Pirmagomedov, Srikathyayani Srikanteswara, Felipe Andrés Tampier Jara, Gabriel Arrobo, Dmistri Moltchanov, Yi Zhang, Nageen Himayat, Sergey Andreev, Yevgeni Koucheryavy
Filed: 3 Nov 21
Utility
chylyi5vxqa5bikbyx3ueq21 k3f6z6zhoc0snbw8
4 Jan 24
Structures having memory access transistors with backside contacts are described.
Abhishek Anil SHARMA, Tahir GHANI, Anand S. MURTHY, Wilfred GOMES, Cory WEBER, Rishabh MEHANDRU, Sagar SUTHRAM, Pushkar RANADE
Filed: 30 Jun 22
Utility
yacz2j164vhb6qq7 dfcr8ooto9dmzuu3
4 Jan 24
The present disclosure is directed to a printed circuit board having a first surface and providing a signal pathway using a plurality of plated through hole (PTH) vias including a first set of PTH vias having a first PTH via coupled to a second PTH via and a first vertical separator being configured therebetween, with the first vertical separator extending a first depth from the first surface, and a second set of PTH vias having a third PTH via coupled to a fourth PTH via and a second vertical separator being configured therebetween, with the second vertical separator extending a second depth from the first surface, and a connector trace coupling the second PTH via to the third PTH via being positioned at a third depth from the first surface, for which the third depth is less than the first depth or the second depth.
Jackson Chung Peng KONG, Bok Eng CHEAH, Kok Hou TEH
Filed: 4 Jul 22
Utility
137wqdli8me64r6we5tw38zve6
2 Jan 24
Embodiments described herein provide a processing apparatus comprising compute logic to train a convolutional neural network (CNN) to perform autonomous re-localization for a service robot or mobile device.
Zhongxuan Liu
Filed: 3 Sep 21
Utility
2xfujv17 02z91axwmimjet2zf4r5z7myz3gu6wi2v1vye2whdbed2jmbix
2 Jan 24
Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request.
Monam Agarwal, Anand K. Enamandram, Wei Chen, Kerry Vander Kamp, Robert A. Branch, Yen-Cheng Liu
Filed: 16 Dec 21
Utility
o6msn3oas5csf9 uxcb19z8aby0ss3g
2 Jan 24
Methods, apparatus, systems, and articles of manufacture to detect the location of sound sources external to computing devices are disclosed.
Hector Cordourier Maruri, Adam Kupryjanow, Karol Duzinkiewicz, Jose Rodrigo Camacho Perez, Paulo Lopez Meyer, Julio Zamora Esquivel, Alejandro Ibarra Von Borstel, Jonathan Huang
Filed: 26 Jun 20
Utility
cvong7n4xyl7jp2wah8vd0r1bybm6j4 j8499tjpoedk7hdhgewi8nvr
2 Jan 24
The technology disclosed herein determining one or more vulnerable instructions in workload code and determining one or more additional instructions to be inserted in the workload code based at least in part on a power model of a system bus of a processor, when a power model of a processor is dependent on an order of instructions of workload code, inserting the one or more additional instructions with dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions; and when the power model is not dependent on the order of instructions of workload code, inserting the one or more additional instructions without dependency to the workload code to produce complementary power consumption of the system bus to power consumption of the system bus from executing the one or more vulnerable instructions.
Abhishek Chakraborty, Chen Liu, Jason Fung, Neer Roggel
Filed: 4 Aug 22
Utility
zca v1frtxmdwzjic3lu23f2df05s15g66svfegy920gjf
2 Jan 24
An apparatus includes a processor, persistent memory coupled to the processor, and a memory protection logic.
Siddhartha Chhabra, Hormuzd M. Khosravi
Filed: 26 Jun 20
Utility
phtjbnyyqky597mki88qq69ntwpsqgivk19cxtvez8dbusdp1dhwsp6bqj56
2 Jan 24
Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure.
Debendra Das Sharma
Filed: 14 Nov 17
Utility
l9vbe608dbbjcsvh6ohai7er0ia9xju
2 Jan 24
An apparatus to facilitate permissions at a computing system platform is disclosed.
Prashant Dewan, Nivedita Aggarwal
Filed: 23 Dec 20